LMG3100EVM-089: LMG3100EVM-089 (Low side FET U5 - LMG3100R017 is shorted after pulse testing)

Part Number: LMG3100EVM-089
Other Parts Discussed in Thread: LMG3100R017

Hello TI support team,

I purchased the LMG3100EVM-089 directly from TI and have been using it for pulsed load testing. One of the two LMG3100R017 devices (U5, low-side) has failed shorted, and I'm trying to understand the likely cause.

Setup:

  • Board: LMG3100EVM-089 (purchased from TI)
  • Bus voltage (VIN): swept 40 - 70V during characterization
  • VCC supply: 7V external (within board's 5.5 - 10V range)
  • Test signal: pulsed, 10kHz repetition rate, duty cycle swept from 0.25% to 2.5% (pulse widths ~250ns to 2.5µs)
  • Load: 0.5ohm resistive (2x Ohmite TEH100M1R00FE 1ohm, 100W in parallel)
  • Scope: LeCroy WavePro 725Zi

Test Timeline:

  1. Day 1: Clean SW node waveform, correct pulse width, and correct average current reading on the supply's front-panel monitor across the duty cycle sweep.
  2. Day 2 morning: Waveform still clean and correct pulse width, but average current reading no longer matched the expected value for the set duty cycle. At the time we suspected the load resistor.
  3. Day 2 afternoon: Powering VCC (J3) and VIN (J1) independently, with no PWM drive active, both supplies unexpectedly entered CC (constant current) mode, indicating a low-impedance fault path even with the FETs not being switched.
  4. We confirmed with a multimeter (board unpowered) that VIN showed a low resistance path to ground.
  5. By selectively removing the VCC feed resistors to each device (R5 for U1, R8 for U5) and re-testing VIN power alone, we isolated the fault to U5 (low-side): removing R8 (cutting VCC to U5) eliminated the CC-mode fault; removing R5 (cutting VCC to U1) did not.

Scope data from before the failure: At 70V bus: SW node top ≈76.9V max, 65.24V top, min ≈-5.5V, rise 4.3ns, fall 9.2ns
My questions are as following:

  • Vin and VCC both stayed within absolute max ratings in our captures, what could cause a sudden short with no apparent overstress?
  • We used 10kHz pulsed operation (250ns–2.5µs pulses), but the EVM is rated for 100kHz–500kHz continuous switching. Could this lower-frequency, pulsed usage be outside the validated envelope and contribute to failure (e.g., bootstrap refresh issues)?
  • Any known failure modes for low-side (U5) VCC/gate-drive or power sequencing we should check?
  • Since this was purchased directly from TI, is there a warranty/replacement path?

Thank you so much in advance. I do appreciate your response. 


Best regards,
May.