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DP83869-SCHEMATIC-CHECKLIST-REVC: X-talk analysis inputs required

Damodara Sanaboyina
Prodigy 30 points

Part Number: DP83869-SCHEMATIC-CHECKLIST-REVC
Other Parts Discussed in Thread: DP83869

Hello Team,

We are using the DP83869HMRGZR in RGMII-to-SGMII bridge mode on our board. Since the board is densely routed, we plan to perform a comprehensive crosstalk (X-talk) analysis across the PCB.

To establish appropriate pass/fail criteria for the analysis, could you please provide the recommended crosstalk limits, noise tolerance levels, raise time/fall time or any signal integrity guidelines applicable to the DP83869HMRGZR, particularly for sensitive interfaces such as SGMII, RGMII, clock, and other high-speed signals?

Any guidance on acceptable victim-noise levels, near-end/far-end crosstalk limits, or recommended SI validation criteria would be greatly appreciated.

Thank you.

Best Regards,
Damodara S

  • 0
    TI__Mastermind 39075 points

    Hi Damodara,

    We do not have specific crosstalk limits for these interfaces. The SI validation criteria we typically look for is as follows:

    RGMII

    • Ensure the setup and hold timings are met at the PHY RGMII receivers (TX_CLK, TXD0/1/2/3, TX_CTRL,...). There will be a similar setup and hold timing for the MAC receivers which will also need to be met.
    • The DP83869 has controls to tune the RX and TX CLK shift for the RGMII to make these timings easier to meet.
    • Make sure the RGMII signals are routed at 50 ohm impedance and use minimal vias on these lines. RGMII signals should be length matched to within 20mils of the relative CLK (RX signals matched to RX_CLK trace, TX Signals to TX_CLK)
    • Rise time and fall time of signals is typically around 750ps - 1ns. up to 1.5ns may be ok as well, though closer to 1ns would be better.

    SGMII

    • Route traces with 100ohm differential impedance 
    • Length match P/N traces to within 5 mils of eachother

    XI reference clk

    Best,

    Shane