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LSF0108-Q1: I2C

Juan Jacinto Montenegro
Prodigy 240 points

Part Number: LSF0108-Q1

Hello, I am Juan from Rother.

We are designing a custom PCB using the LSF0108-Q1 bidirectional voltage-level translator to interface the 1.8 V I2C signals with a 3.3 V I2C bus.

We need to determine the appropriate pull-up resistor values for SDA and SCL on the B side of the LSF0108-Q1.

In Section 9.2.1.2.2 of the datasheet, TI recommends sizing the pull-up resistors to limit the current through the internal pass transistor to approximately 15 mA. However, the datasheet also provides resistor values for lower currents, including 8 mA, 5 mA and 3 mA.

Since our application uses standard open-drain I2C signals, we would like to clarify the recommended design approach for this application.

Could you please clarify the following points?

  1. Recommended current: What current should we target when sizing the pull-up resistors for SDA and SCL when using the LSF0108-Q1 for a 1.8 V to 3.3 V I2C interface? Would designing for approximately 3 mA through the translator be appropriate for this application?

  2. Pull-up resistor calculation: Is the equation provided in the datasheet intended as a maximum-current design criterion, or should the recommended resistor values in Table 9-4 be considered the preferred starting point for I2C applications?

  3. Pull-ups on both sides: When pull-up resistors are installed on both the A and B sides, how should the total current be evaluated to ensure that the I2C devices can maintain a valid LOW level? We would particularly appreciate clarification regarding the current that must be sunk by the devices connected to the bus versus the current flowing through the LSF0108-Q1 pass transistor.

  4. Recommended implementation: For a 1.8 V / 3.3 V I2C interface, are there any specific pull-up resistor values or design recommendations you would suggest for reliable operation with the LSF0108-Q1?

Our objective is to select suitable resistor values that ensure valid logic levels and compliant I2C rise times without unnecessarily increasing the current drawn when either line is LOW.

Thank you for your assistance.

Best regards,
Juan

  • +1
    TI__Intellectual 1810 points

    Hi Juan,

    For I2C, the pull-up current is set by two external constraints, not by the LSF0108-Q1. The VOL / sink-current capability of the weakest device on the bus, and the rise time needed for your I2C speed, given total bus capacitance. Targeting for a few mA is a good start provided your rise-time budget is met.

    For I2C, pull-ups are required on both the A and B sides. A driver pulling the line low sinks its own side's pull-up current plus the opposite side's pull-up current conducted through the pass transistor. The pass transistor adds some series resistance in that path. That IR drop raises the far-side LOW level above the driver's VOL, so the receiving device's VIL margin must be checked at your chosen current, not just the driver's VOL. This is the main reason for keeping per-line current modest, doubling the pull-up current doubles the sink burden on every device on the combined bus.

    A common configuration for 1.8V to 3.3V translation is using 2.2k Ohms on both sides and adjusting from there. More information and guidance for sizing PU resistors for an I2C bus can be found in this app note.

    Regards,

    Jason