Hi,
I have been trying to simulate TLV1117LV18 using Cadence Pspice with the help of TI's Pspice model.
I was trying to simulate my real design which has a load that draws ~1A from TLV1117LV18.
The simulation shows, the input voltage (3.7v) is dropping even for 50% load i.e load that sinks ~500mA.
The Vin stays stable only for load current close to 0mA. This will not be the real scenario.
So I would like to know what could be the issue.
Herewith I have attached the sim ckt and results embedded in the ckt page for your reference.
Please do the needful.
Regards,
Karthik3312.TLV1117LV18_SIM.pdf
