Hello everyone,
I need to test BUZ901/906 pair of devices in an LM4702 based application, I've got this models (attached) from a member of diyaudio (www.diyaudio.com), but I don't know how to use them with TINA.
I've also another problem because I can't simulate the current between sink and source pins using the LM4702 model from TI.
Thank you very much for your attention,
Best regards,
Daniel Almeida
.SUBCKT BUZ901P 1 2 3 * MODEL FORMAT: SPICE Level 1 * External Node Designations * Node 1 -> Drain * Node 2 -> Gate * Node 3 -> Source M1 9 7 8 8 MM L=0.001 W=0.001 * Default values used in M: * The capacitances are added externally * Other default values are: * RS=0 RD=0 LD=0 CBD=0 CBS=0 CGBO=0 .MODEL MM NMOS LEVEL=1 IS=1e-32 +VTO=0.473 LAMBDA=0.092 KP=1.585 RS 8 3 0.41 D1 8 9 MD .MODEL MD D IS=1.0e-32 N=50 BV=250 +CJO=1.0e-9 VJ=0.7 M=0.5 RDS 8 9 1e+06 RD 9 1 0.58 RG 2 7 80 * Gate Source capacitance Cgs0 CAP1 7 8 400e-12 ************************* * Gate Drain capacitance Cdg0 CAP 7 4 10.5e-12 ************************* * Gate Drain Capacitance Cdgj0 * Modelled as a diode D2 4 9 MDD .MODEL MDD D IS=1e-32 N=50 +CJO=94.8e-12 VJ=0.3 M=1 ************************* .ENDS BUZ901P .SUBCKT BUZ906P 1 2 3 * MODEL FORMAT: SPICE Level 1 * External Node Designations * Node 1 -> Drain * Node 2 -> Gate * Node 3 -> Source M1 9 7 8 8 MM L=0.001 W=0.001 * Default values used in M: * The capacitances are added externally * Other default values are: * RS=0 RD=0 LD=0 CBD=0 CBS=0 CGBO=0 .MODEL MM PMOS LEVEL=1 IS=1e-32 +VTO=-0.426 LAMBDA=0.073 KP=0.673 RS 8 3 0.342 D1 9 8 MD .MODEL MD D IS=1.0e-32 N=50 BV=250 +CJO=1.45e-9 VJ=0.446 M=0.377 RDS 8 9 1e+06 RD 9 1 0.523 RG 2 7 45.2 * Gate Source capacitance Cgs0 CAP1 7 8 696e-12 ************************* * Gate Drain capacitance Cdg0 CAP 7 4 15.2e-12 ************************* * Gate Drain Capacitance Cdgj0 * Modelled as a diode D2 9 4 MDD .MODEL MDD D IS=1e-32 N=50 +CJO=27.6e-12 VJ=0.817 M=0.871 ************************* .ENDS BUZ906P
