I have an issue when checking a design using the two design packages - my design TPS40055 30V to 7V @ 10A in switcherpro provides me with significantly lower thermal stress for the sync FET than TPS40K software, independent calculations support the figures from TPS40K or show higher losses.
Also the Switcherpro is pessimistic on the number of FETs which can be safely driven (SI7116DN)
Is there a problem with the FET model or Switcherpro software?
Ed