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TPS40057 problem! Please help!

Krisztian Kocsis
Prodigy 70 points
Other Parts Discussed in Thread: TPS40057

Hi! I have built a DC/DC converter with a TPS40057 based on my design (ID: 38122). Unfortunatelly it is not working, it outputs about 5V ~ 8V instead of 12V, and it is swinging.

I have redesigned the compensation components according to the current data sheet of the device. Now it is working (outputs 11.98V), but sometimes the output goes bellow to 8-9V for 10-20 seconds.

The load typically drains 1.5A. I also had to add a snubber, because it didn't get wokring until I have added. Peaks were very big (45-50V). According to the application note on how to design a snubber, i have found the value of parasitic cap. and inductance of the borad.

The second problem is that the application note says that i have to add Cpara * 3 or greater value of cap. to enough reduction to the peaks. The design has about 310 pF parasitic capacitance. If I add a 910pF cap. the peaks are reduced by 5-7V, but if I add an 1nF cap. the oscillation won't start (I see 4-5V DC with my scope on SW node). It is bigger, but where is the problem? Why the voltage isn't 12V at the output with the original design.

Please give me some suggestions!

Design ID: 38122, application note: SLVA255.

Note: I use 1uF caps for C3 and C4 and Si4840BDY (i can't get Si4840DY because Vishay says that this FET is obsolote and replaced with Si4840BDY - very very similar).

Thanks for your help!

  • TI__Intellectual 2710 points

    Thank you for posting this issue. We will look into it and will update you.

  • in reply to Hetal
    TI__Intellectual 2710 points

    Your design is showing 20dB of gain from the output to the control voltage (compensated error amplifier) which is excessive and may be resulting in the oscillations.

     

    Your current limit resistor is very low.  This appears to be due to the selection of a 9mOhm high-side FET for a 3.2A power supply thus designing for about a 28mV current limit. 

     

    Higher efficiency could almost certainly be achieved with a higher Rdson MOSFET that has lower switching losses at this low current.  According to the stress page, this MOSFET has about 70mW of conduction losses and 620mW of total losses for 550mW of switching losses.  These two should be approximately equal to achieve the best efficiency.  I would look for an 18-20mOhm high-side FET which would increase the current limit resistor significantly.

     

    Analysis also shows the UVLO level at 12.8V, which is too low to support a 12V output so the current limit resistor R7 should be increased to increase the UVLO level.

     

    It would really help if someone can look at oscillograms, a layout and more data.  Can you please get in touch with the local TI AFA (Analog Field Applications Engineer).  If you have voltages >55V on your switch node for a 32V input, you also have layout issues and they may be more involved than we can determine from looking at the switcher pro schematic.

    Thanks,

    Hetal.