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TPS54160 design using SwitcherPro

Other Parts Discussed in Thread: TPS54160

Hello, Please advice about TPS54160 design using SwicherPro on line.

I designed TPS54160 circuit which Vin=4.5 - 36V, Vout=3.3V, Iout=0.5A as follows. Loop Response page showed Phase Margin=84 Deg.

But today(2010.1.6) I re-design the same circuit using SwitcherPro on line, it shows Phase Margin 43 deg with "Low Phase Warning". Would you know what occors ?  

 

  • Can you send me the files?  From the notes page you can send the file to me at my emai address

  • John-san,
     
    I attach the files.
     
      DSN_TPS54160_3.3V0.5A.pdf               // Phase Margin = 84 Deg.
      DSN_TPS54160_3.3V0.5A_2010_0106.pdf     // Phase Margin = 43 Deg.
     
    I believe both circuits are almost same.
    And I think the Power Stage Gain shown on DSN_TPS54160_3.3V0.5A_2010_0106.pdf
    is not natural as a current control DC/DC.
     
    Best regards,
    Kazuaki Ohshita


    From: JohnTucker [mailto:noreply@e2e.ti.com]
    Sent: Tuesday, January 12, 2010 7:19 AM
    To: switcherpro@e2e.ti.com
    Subject: Re: [SwitcherPro Forum] TPS54160 design using SwitcherPro

    Can you send me the files?  From the notes page you can send the file to me at my emai address


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    View this message online at http://e2e.ti.com/support/specialty_analog/analog_elab_and_tools/f/235/p/31217/109842.aspx#109842 or reply to this message
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  • John-san,
     
    How are you. I'm Kazuaki Ohshita.
     
    How is the progress about below question?
    If I need to do some action, please let me know.
     
    Best regards,
    Kazuaki Ohshita


    From: a0730072 [mailto:noreply@e2e.ti.com]
    Sent: Tuesday, January 12, 2010 9:42 AM
    To: switcherpro@e2e.ti.com
    Subject: RE: [SwitcherPro Forum] TPS54160 design using SwitcherPro

    John-san,
     
    I attach the files.
     
      DSN_TPS54160_3.3V0.5A.pdf               // Phase Margin = 84 Deg.
      DSN_TPS54160_3.3V0.5A_2010_0106.pdf     // Phase Margin = 43 Deg.
     
    I believe both circuits are almost same.
    And I think the Power Stage Gain shown on DSN_TPS54160_3.3V0.5A_2010_0106.pdf
    is not natural as a current control DC/DC.
     
    Best regards,
    Kazuaki Ohshita


    From: JohnTucker [mailto:noreply@e2e.ti.com]
    Sent: Tuesday, January 12, 2010 7:19 AM
    To: switcherpro@e2e.ti.com
    Subject: Re: [SwitcherPro Forum] TPS54160 design using SwitcherPro

    Can you send me the files?  From the notes page you can send the file to me at my emai address


    --
    View this message online at http://e2e.ti.com/support/specialty_analog/analog_elab_and_tools/f/235/p/31217/109842.aspx#109842 or reply to this message
    Capture this message to a wiki


    --
    View this message online at http://e2e.ti.com/support/specialty_analog/analog_elab_and_tools/f/235/p/31217/109895.aspx#109895 or reply to this message
    Capture this message to a wiki

  • I checked this design with the online switcherpro.  I got a completely different schematic and result with 70 deg of phase margin.  I will forward this to the software design team.  Theoretically you should get the same result from teh same inputs.  Did you change anything or just enter the simple inputs and let the software generate the design? 

  • Let me explain the problem. It is not phase margine issue, the problem is unnatural design of TPS54160/54060 using latest version of SwitcherPro.  Please compare the bode diagrams of "DSN_TPS54160_3.3V0.5A.pdf" and "DSN_TPS54160_3.3V0.5A_2010_0106.pdf" which are sent previously. "DSN_TPS54160_3.3V0.5A_2010_0106.pdf" is designed by latest version of SwitcherPro and the bode-diagram on it seems to be unnatural. These circuits are designed using "Simple inputs", and L, Cout and phase compensation C/R are modified. 

    Simply, we can design a TPS54160 circuit Vin=4.5V to 36V, Vout=3.3V, Iout=0.5A using latest SwitcherPro, and the default result shows 70 deg of phase margine, but the cross over frequency is only 4.8KHz and the bode diagram is unnatural. The power stage gain on the diagram is like the gain of 2'nd order LPF.  Since TPS54160/54060 is current mode DC/DC and the plant model should be close to 1'st order circuit, not 2'nd order circuit.

    So, would you please check the behavior of TPS54160/54060 design using latest SwitcherPro?

     

  • The graphs are generated with Vin = minimum so in that case the duty cycle is somewhat high and there is a fair amount of slope compensation added in.  Slope compensation makes the powerstage gain take omore of a voltage mode characteristic with the roll of greater than -20 dB / decade and teh phase decreases fastera as well.  The powerstage plots look correct.

  • I spent some time looking at this and I think I've figured out what happened.

    I took the parameters from the first design and built a design in SwitcherPro today.  Then I replaced the componenets from today's design with the users original values.

    From there I loaded up the "What if Analysis"

    These plots attache are from  the same design with different conditions on the model. (you can do that from what if analysis, under "conditions" tab)

    First test, VinMin and IoutMax,   Second (lower) image is VinMax and IoutMin

    So you can see that both responses are correct for this design.  The problem was that back in 2008 even though switcherpro claimed that it was showing the default plot of VinMinum and Iout Maximum it wasn't.  Sometime in Early 2009 this bug got fixed and we actually started plotting the default loop response graph with the correct conditions, of VinMinimum and IoutMaximum,  that explains the change in the response, even though the model is still the same.

    I hope this helps

     

  • John-san, Heath-san,

    Thank you very much for your kind explanations.

    Now, I understand the TPS54160/54060 behavior by conditions and got the same result sent by Heath-san using "What if analysis".

    Thanks again, Kazuaki Ohshita