This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

LM5118 PSPICE reference simulation not converging

Other Parts Discussed in Thread: LM5118

Hello,

   I'm running TI's PSPICE reference design for the LM5118 steady-state model (Using PSPICE 16), and it's not converging.  I'm not sure how to fix this; any suggestions?

Here's the log:

**** 08/07/14 19:55:45 ***** PSpice 16.6.0 (October 2012) ***** ID# 0 ********

** Profile: "STEADY_STATE-STEADY_STATE" [ E:\LM5118 PSPICE\lm5118_trans-pspicefiles\steady_state\steady_state.sim ]


**** CIRCUIT DESCRIPTION


******************************************************************************


** Creating circuit file "STEADY_STATE.cir"
** WARNING: THIS AUTOMATICALLY GENERATED FILE MAY BE OVERWRITTEN BY SUBSEQUENT SIMULATIONS

*Libraries:
* Profile Libraries :
* Local Libraries :
.LIB "../../../lm5118_trans.lib"
* From [PSPICE NETLIST] section of C:\Users\mhwang\AppData\Roaming\SPB_Data\cdssetup\OrCAD_PSpice/16.6.0/PSpice.ini file:
.lib "nom.lib"

*Analysis directives:
.TRAN 0 4.18m 4.16m 80n SKIPBP
.OPTIONS ADVCONV
.OPTIONS ABSTOL= 1E-08
.OPTIONS GMIN= 1.0E-11
.OPTIONS ITL1= 1000
.OPTIONS ITL2= 2000
.OPTIONS ITL4= 100
.OPTIONS RELTOL= 0.01
.OPTIONS VNTOL= 1E-05
.PROBE64 V(alias(*)) I(alias(*))
.INC "..\STEADY_STATE.net"

**** INCLUDING STEADY_STATE.net ****
* source LM5118_TRANS
R_Rsource N212699 VIN 50m TC=0,0
V_Vin1 N212699 0
+PWL 0 0 1u 16.5 4.18m 16.5
V_V_Iinductor N315125 SW2 0Vdc
R_R3 0 N315029 6.49K TC=0,0
X_D1 SW2 VOUT MBRD1035
R_R12 N315219 VOUT 8.66k TC=0,0
X_D1_1 SW2 VOUT MBRD1035_1
R_R7 0 N315109 18.7K TC=0,0
C_C15 0 N315181 0.39n TC=0,0
C_C16 0 N315197 22n TC=0,0
R_R9 N315219 0 1k TC=0,0
C_C7 VOUT 0 1000n TC=0,0
R_R4 COMP N315339 17.4K TC=0,0
C_C18 N315219 N315339 10n TC=0,0
X_COUT N315491 0 COUT PARAMS: IC=0 C=200u ESR=0.012
V_V_Icout VOUT N315491 0Vdc
C_C17 COMP N315219 0.56n TC=0,0
V_V_Iout VOUT N315669 0Vdc
C_C20 0 N315371 1000n TC=0,0
R_R13 N314957 0 0.015 TC=0,0
X_Q1 VIN N315477 SW1 Si7148_Q1
X_L1 N315125 SW1 L1 PARAMS: IC=0 L=10u DCR=0.0255
X_D4 N314957 SW1 UB0100C
X_D4_1 N314957 SW1 UB0100C_1
C_C8 N315495 SW1 100n TC=0,0
X_CIN VIN 0 CIN PARAMS: IC=0 C=44u ESR=0.025
X_U1 VIN N315029 N315109 N314997 N315181 N315197 N315219 COMP VOUT 0 0
+ N314957 N315515 N315495 N315477 SW1 N315371 VOUT LM5118_TRANS
R_R1 N315029 VIN 27.4K TC=0,0
X_Q2 SW2 N315515 0 Si7148_Q2
R_R2 N314997 VIN 1MEG TC=0,0
C_C6 0 VIN 100n TC=0,0
R_Rload 0 N315669 4 TC=0,0

**** RESUMING STEADY_STATE.cir ****
.END
Reducing minimum delta to make the circuit converge.
Reducing minimum delta to make the circuit converge.
Reducing minimum delta to make the circuit converge.

ERROR(ORPSIM-15138): Convergence problem in transient analysis at Time = 157.9E-12.
Time step = 305.2E-21, minimum allowable step size = 1.000E-18

These voltages failed to converge:

V(X_U1.XA29.YINT) = 404.16uV \ 2.485pV

These supply currents failed to converge:

I(X_U1.XA29.E_ABMGATE) = -404.16uA \ -2.485pA

These devices failed to converge:
X_U1.XA_loqset.E_ABMGATE X_U1.XA_loqrst.E_ABMGATE X_U1.XA21.E_ABMGATE1
X_U1.XA250n.E_ABMGATE1 X_U1.XA_pwmset.E_ABMGATE X_U1.XA29.E_ABMGATE
X_U1.XA_pwmrst.E_ABMGATE X_U1.XA32.E_ABMGATE1

Last node voltages tried were:

NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE


( SW1) 18.02E-06 ( SW2) 12.29E-12 ( VIN) 45.51E-06 ( COMP) 152.0E-06

( VOUT) 1.938E-12 (X_L1.3) 18.03E-12 (N212699) .0026

(N314957) 1.444E-06 (N314997) 45.51E-12

(N315029) 8.716E-06 (N315109) .0187

(N315125) 12.29E-12 (N315181) .0019

(N315197) .0352 (N315219) 152.0E-06

(N315339) 152.0E-06 (N315371) 901.3E-09

(N315477) 21.46E-06 (N315491) 1.938E-12

(N315495) 18.02E-06 (N315515) 1.010E-12

(N315669) 1.938E-12 (X_CIN.3) 45.51E-06

(X_Q1.21) 45.51E-06 (X_Q1.d2) 45.10E-06

(X_Q1.g2) 21.46E-06 (X_Q1.s2) 18.06E-06

(X_Q2.d2) 11.22E-12 (X_Q2.g2) 1.010E-12

(X_Q2.s2) 74.14E-15 (X_U1.V7) 7.0000

(X_COUT.3) 1.938E-12 (X_U1.CLK) .3000

(X_U1.CSi) .0180 (X_U1.CSo) .1978

(X_U1.DRV) 1.7500 (X_U1.loQ) 1.7500

(X_U1.tst) 0.0000 (X_U1.CLK1) .3000

(X_U1.CSGi) .0182 (X_U1.loQN) 1.7500

(X_U1.PWMQ) 1.7500 (X_U1.conv3)-4.657E-06

(X_U1.CSout)-59.43E-06 (X_U1.HIrst) 2.960E-12

(X_U1.Lorst) 0.0000 (X_U1.oscQN) .4969

(X_U1.pkrmp) 1.0012 (X_U1.PWMQN) 1.7500

(X_U1.SSmax) .1502 (X_U1.SSmin) .0070

(X_U1.unsat) 3.4999 (X_U1.clkdly) .0012

(X_U1.CSoffs) .2000 (X_U1.curlim) 1.4500

(X_U1.CURrst) 0.0000 (X_U1.DRVdly) 0.0000

(X_U1.enable) .1500 (X_U1.erramp) .5104

(X_U1.gateHI) -.0138 (X_U1.gateLO) -.0686

(X_U1.ground) 0.0000 (X_U1.LDOctl) 50.0000

(X_U1.logic1) 901.3E-09 (X_U1.Lorst2) 0.0000

(X_U1.maxerr) .5104 (X_U1.minTon) 0.0000

(X_U1.REGctl) 0.0000 (X_U1.regout) 23.21E-06

(X_U1.rstloQ) 0.0000 (X_U1.rstPWM) 0.0000

(X_U1.sawCTL) 0.0000 (X_U1.SCSctl) -.0195

(X_U1.setloQ) 1.7500 (X_U1.setPWM) 1.7500

(X_U1.SSclmp) .1502 (X_U1.trigon) 0.0000

(X_U1.Vccgen) 901.3E-09 (X_U1.VccTST) 45.51E-06

(X_U1.Vccval) 901.3E-09 (X_U1.Vstart) 45.47E-09

(X_U1.endTonA) .2091 (X_U1.erramp1) 152.0E-06

(X_U1.initrst) 1.7500 (X_U1.triggen) .0275

(X_U1.trigger) 0.0000 (X_U1.trigoff) 0.0000

(X_U1.tst_int) 0.0000 (X_U1.endBOOST) -1.0000

(X_U1.sawtooth) 0.0000 (X_U1.SRampctl) .0020

(X_U1.XA6.YINT) 0.0000 (X_U1.XA7.YINT) 0.0000

(X_U1.XVCOA1.3) 3.0553 (X_U1.XVCOA1.4) 4.0000

(X_U1.XVCOA1.5) -4.0000 (X_U1.XVCOA1.6)-409.3E-06

(X_U1.XVCOA1.7) -2.0000 (X_U1.boostmode) 0.0000

(X_U1.bstCLKinv) 1.7500 (X_U1.bstminTon) 0.0000

(X_U1.DriveBuck) 0.0000 (X_U1.genPWMrst) 0.0000

(X_U1.narrowctl) 0.0000 (X_U1.XA13.YINT) 0.0000

(X_U1.XA14.YINT) 0.0000 (X_U1.XA15.YINT) 0.0000

(X_U1.XA16.YINT) 0.0000 (X_U1.XA18.YINT) 3.5000

(X_U1.XA19.YINT) 0.0000 (X_U1.XA20.YINT) 3.5000

(X_U1.XA21.YINT) 3.4996 (X_U1.XA22.YINT) 0.0000

(X_U1.XA26.YINT) 0.0000 (X_U1.XA28.YINT) 3.5000

(X_U1.XA29.YINT) 404.2E-06 (X_U1.XA30.YINT) 0.0000

(X_U1.XA32.YINT) 3.4996 (X_U1.XA33.YINT) 3.5000

(X_U1.XA37.YINT) 3.5000 (X_U1.buckCLKinv) 1.7500

(X_U1.DriveBoost) 0.0000 (X_U1.DriveBuckA) -.0020

(X_U1.EmulatedIL) .0022 (X_U1.XA_DFF.MY5) 3.5000

(X_U1.XA_DFF.Qbr) 3.5000 (X_U1.XA_DFF.Qqq) .7894

(X_U1.DriveBoostA) -.0098 (X_U1.enable_init) .3000

(X_U1.HSmagnified) -.0018 (X_U1.SCSctl_init) -1.0000

(X_U1.XA200n.YINT) .3000 (X_U1.XA_DFF.Qint) .7894

(X_U1.rmpplusdiode) 1.1876 (X_U1.XA250n.YINT1) 0.0000

(X_U1.XA250n.YINT2) 0.0000 (X_U1.XA250n.YINT3) 0.0000

(X_U1.XA_DFF.MYVSS) 0.0000 (X_U1.XA_DFF.Qqqd1) .0386

(X_U1.DriveBuckAint) -1.0000 (X_U1.XA_DFF.CLKdel) .4969

(X_U1.XA_DFF.CLKint) 0.0000 (X_U1.XA_DFF.X2.YINT) 0.0000

(X_U1.XA_loqrst.YINT) 3.4996 (X_U1.XA_loqset.YINT) 3.4992

(X_U1.XA_minTon.YINT) 0.0000 (X_U1.XA_pwmrst.YINT) 3.4996

(X_U1.XA_pwmset.YINT) 3.4992 (X_U1.XA_Toggle.YINT) 0.0000

(X_U1.CS2CSGmagnified) -.0014 (X_U1.XA_DFF.X1.YINT1) 0.0000

(X_U1.XA_DFF.X1.YINT2) 0.0000 (X_U1.XA_DFF.X1.YINT3) 3.5000

(X_U1.XA_DFF.X3.YINT1) 0.0000 (X_U1.XA_DFF.X3.YINT2) 0.0000

(X_U1.XA_DFF.X3.YINT3) 0.0000 (X_U1.DriveBoostA_init) -1.0000

(X_U1.XA_400ns_dlyx.YINT1) 0.0000 (X_U1.XA_400ns_dlyx.YINT2) 0.0000

(X_U1.XA_400ns_dlyx.YINT3) 0.0000


**** Interrupt ****

  • Hi Michael,

    What is your VNTOL and ABSTOL settings currently? Can you increase it by a magnitude of 10 each and see if it resolves the problem. If that does not work, can you send us your design files?

    Thanks,

  • MichaelH,

    I have confirmed that the reference design works correctly in version 16.2, however, it does not converge in 16.6. I am not sure why the newer version does not work the same as the previous version. In order to get the simulation to run peoperly, please change the Maximum step size from 80n to 20n:

    And set the following options:

    RELTOL from 0.01 to 0.001, Transient time point iteration from 100 to 1000, and check the Use perordering to reduce... box:

    The simulation should now run correctly as it does in 16.2.

    Britt