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Hi,
we're planning to use the LM5116 for a non-isolated power supply. After downloading the pspice transient model and starting the simulation in PSPICE version 16.0, I get the following output:
**** 09/29/14 11:13:34 ******* PSpice 16.0.0 (July 2006) ****** ID# 0 ******** ** Profile: "Startup-trans" [ E:\Notes\PowerSupply\PSPICE\LM5116_PSPICE_TRANS\lm5116_trans-pspicefiles\startup\trans.sim ] **** CIRCUIT DESCRIPTION ****************************************************************************** ** Creating circuit file "trans.cir" ** WARNING: THIS AUTOMATICALLY GENERATED FILE MAY BE OVERWRITTEN BY SUBSEQUENT SIMULATIONS *Libraries: * Profile Libraries : * Local Libraries : .LIB "../../../lm5116_trans.lib" * From [PSPICE NETLIST] section of C:\OrCAD\OrCAD_16.0\tools\PSpice\PSpice.ini file: .lib "nom.lib" *Analysis directives: .TRAN 0 2.2m 0 4n SKIPBP .OPTIONS ABSTOL= 10n .OPTIONS ITL1= 1500 .OPTIONS ITL2= 1000 .OPTIONS ITL4= 1000 .OPTIONS RELTOL= 0.003 .OPTIONS VNTOL= 1u .PROBE V(alias(*)) I(alias(*)) .INC "..\Startup.net" **** INCLUDING Startup.net **** * source LM5116_TRANS R_R4 0 FB 1.21k C_C22 0 VIN 47u IC=0 V_V1 N146406651 0 +PULSE 0 48 100u 10u 10u 1 3 R_Rload 0 OUT {12/5} X_Q2 SW LO CS M1_NMOS R_R3 OUT FB 10.7k C_C11 0 VIN 2.2u C_C6 FB N14640359 1.5n R_R12 VCCX OUT 1 C_C9 0 VIN 2.2u R_R10 N14640359 COMP 39k R_R2 0 UVLO 9.31k C_C7 UVLO 0 1n IC=0 D_D2 UVLO VIN myD27227 C_C8 0 VIN 2.2u X_L1A SW OUT LDCR PARAMS: L=10u DCR=5.8m C_C3 SS 0 10n IC=0 D_D1 VCC N14640207 myD27227 C_C5 FB COMP 15p X_C17 0 OUT CESR PARAMS: C=47u ESR=5m IC=0 X_C19 0 OUT CESR PARAMS: C=47u ESR=5m IC=0 R_R11 0 CS 0.01 X_C18 0 OUT CESR PARAMS: C=47u ESR=5m IC=0 C_C12 0 VIN 1u C_C1 SW N14640207 1u X_C16 0 OUT CESR PARAMS: C=47u ESR=5m IC=0 X_C20 0 OUT CESR PARAMS: C=22u ESR=5m IC=0 R_R15 RAMP VCC 750k R_RS N146406651 VIN 50m R_R1 VIN UVLO 102k R_R16 N14640207 HB 2.2 X_Q1 VIN HO SW M1_NMOS C_C4 0 RAMP 330p C_C2 VCC 0 1u IC=0 C_C10 0 VIN 2.2u C_C14 0 VCCX 1u C_C13 VIN 0 0.1u R_R13 VIN EN 1MEG R_R9 0 RT/SYNC 12.4k X_U1 VIN UVLO RT/SYNC EN RAMP 0 SS FB COMP OUT 0 CS 0 0 LO VCC VCCX HB + HO SW 0 LM5116_TRANS **** RESUMING trans.cir **** .END Unable to find index file lm5116_trans.ind for library file lm5116_trans.lib Making new index file lm5116_trans.ind for library file lm5116_trans.lib Index has 25 entries from 1 file(s). ERROR -- Invalid model Level for Mosfet X_U1.BSIM3N **** 09/29/14 11:13:34 ******* PSpice 16.0.0 (July 2006) ****** ID# 0 ******** ** Profile: "Startup-trans" [ E:\Notes\PowerSupply\PSPICE\LM5116_PSPICE_TRANS\lm5116_trans-pspicefiles\startup\trans.sim ] **** Diode MODEL PARAMETERS ****************************************************************************** myD27227 IS 1.000000E-15 N .1 RS .05 TT 10.000000E-12 JOB ABORTED **** 09/29/14 11:13:34 ******* PSpice 16.0.0 (July 2006) ****** ID# 0 ******** ** Profile: "Startup-trans" [ E:\Notes\PowerSupply\PSPICE\LM5116_PSPICE_TRANS\lm5116_trans-pspicefiles\startup\trans.sim ] **** JOB STATISTICS SUMMARY ****************************************************************************** Total job time = .03
I changed nothing to the original simulation and there seems to be an error in U1. Please advise how to solve this. Thanks in advance.
Frank,
I have verified that the circuit works correctly in version 16.2. I do not have access to version 16.0 as it is no longer supported by Cadence. The latest version is 16.6 and the simulation works correctly in it as well.
If you do not have access to a later version of PSpice, please consider TI's free simulator TINA-TI. You can download and install it and it will run this reference design.
Britt
Frank,
Please try this .lib file. You will have to download it and rename it to LM5116_TRANS.LIB and replace the existing .lib file. I have not tested this in PSpice version 16.0, however, I believe that it should solve the reported issue. You may wish to change the maximum time step to 20ns as well to speed up the simulation.
Britt