Using Polarised Electrolytic Capcitors without an Low ESR rating with Lm2678 Buck

Hello Tony,

Thanks for using WEBENCH. Please see below comments:

Is it okay to use Ordinary ESR capacitors with the same capacitance rating(or should I increase the value) and whats are the performance setbacks I should take into account if so due to ESR rating?

A: larger ESR will introduce larger voltage ripples at the output. However, stability issue is the main concern here, which is caused by the impact of Capacitor's ESR on the Phase Margin. Larger ESR would increase the value of phase margin. You can observe the effect of ESR on the phase margin by selecting alternative capacitors with different ESR values, and then see the difference undder “Op Vals”. If you are unable to find capacitors with low ESR, you may want to place several smaller capacitors in parallel to achieve the total value of Cout recommended by WEBENCH. This will minimize the overall ESR value.

Is it okay to use capacitors with higher capacitance rating (ESR and Non-ESR) than specified in the Webbench Simulations?

A: Cout selection in WEBENCH is implemented based on optimum performance in terms of stability and voltage ripple. Higher capacitance in the power stage will narrow down the bandwidth (reduces the cut-off frequency). Consequently, if the power stage inductor doesn’t get modified accordingly, the relocation of power stage pole may lead to instability in the system. So, choosing a capacitance larger than what is calculated by WEBENCH is not recommended (unless applying proper change to the inductor’s value).

Will higher capacitance and ordinary ESR affect anything other than the Turn ON time(due to time take to charge in the input and output capacitors)??

A: This question is answered above.


About the di/dt loops in the PCB board, how does it affect if I use a number of Input and Output caps in parallel ( to increase the capacitance) do?

A: Using parallel caps in the PCB board will reduce the effective ESR and inductive parasitic components (ESL). Consequently, the effect of dt/dt in terms of ESL’s voltage spikes will be suppressed.


Regards,
Hadi