Basic design is WEBENCH for 5 to 36V in and 15V at 2A out. WEBENCH will not provide any results if I run dv/dt and set the output current to be low (100mA) at nominal input voltages of 12 or 24V. It does not provide any error messages. I suspect its outside the operating range due to duty cycle restrictions or similar. Is there a way to force WEBENCH to simulate this state or at least provide an error or warning message to guide me on the problem ?. Otherwise its build a prototype and test that which seems to defeat the point of the simulator. Any help gratefully received
Tom,
We will investigate the behavior of the dv/dt panel. As a short term solution, you could use the Schematic Editor and run a startup simulation with your required values. Click on the Edit icon and select the green "Edit this design" button on the lower left hand side of the pop up window. This will create a copy of the WEBENCH® generated design in the Schematic Editor (Startup simulation only, no CC functions supported). Click on the Vin1 input and change it to 12V.
Next, click on the Load (Rload) and change it to 150Ohms (for the 100mA case).
Click on the simulation button (the red sine wave) and run the simulation. You can look at any of the results using the probe list or by simply clicking on the node or component in the schematic.
You can now update Vin to 24V and re-run the simulation. Please remember that this is a simulation only interface. You can always return to the original design by using the MyDesigns link in the WEBENCH® window (upper left hand corner).
