TINA / transient delay between source and output

Hi JJ,

The simulator skips sample time steps during the simulation to save on the amount of data saved and the length of time the simulation takes. To my knowledge, this sample skipping scheme differs from simulator to simulator, but the idea is that the simulator monitors how much the node voltages and currents from one time step snapshot to the next and then adaptively changes the time between samples accordingly. If the voltages and currents have barely changed from one sample to the next, then the simulator will increase the sample time interval (take fewer samples), until big changes are detected again and then the simulator will decrease the sampling time interval to take more samples.
As you are seeing, this adaptive sampling scheme is not always perfect and can cause some undersampling of changes in the signals. For instance, in your example, the simulator takes a sample at 900us where the signal is 1V, but the next sample taken at 1ms is down at 0V, and a straight line is simply drawn between those two samples.
However, you can override the simulator and set a maximum time step allowed in TINA. Go to Analysis->Set Analysis Parameters menu in TINA, and lower the value of the 'TR maximum time step' parameter. For me, the default is 10Gs, but you can change this to something really small like 10us. This will force the simulator to at least take a sample every 10us. You should see the difference in your simulation accordingly.

Regards,
Kris