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Finding TI AFA to set up NDA for unencrypted NextGen FET PSpice models.

Steve Schoenbauer
Prodigy 20 points
Other Parts Discussed in Thread: CSD, CSD16570Q5B, CSD17570Q5B

Hello,

We are interested in completing an NDA to obtain unencrypted PSpice (Level-3) models for NextGen FETs  (CSD 16570 & CSD 17573).

Can you guide us on the process through TI AFA to accomplish this.

Thanks,

-Steve

  • 0
    TI__Mastermind 41310 points

    Steve,

    Let me see what I can find out.

    We normally do not provide a simple Level 3 MOSFET model for the NexFETs as they cannot be well represented by that set of model equations. The PSpice models use a Level 7 based subcircuit that can more accurately represent the behavior of the NexFET devices.

  • 0 in reply to Britt Brooks - Online Design Tools
    Prodigy 20 points

    Hi Britt,

    I found this supplemental info (below) on the MOS models LTSpice uses.  Apparently the model is a rather crude level-3 rendering.

    However, If you could help us obtain the corresponding parameters for the TI   (CSD16570Q5B, CSD17570Q5B)  @25C, we wouid be grateful. Thanks.

    Rg         Gate ohmic resistance
    Rd         Drain ohmic resistance (this is NOT the RDSon, but the resistance of the bond wire)
    Rs         Source ohmic resistance.
    Vto       Zero-bias threshold voltage.
    Kp –      Transconductance coefficient
    Lambda  Change in drain current with Vds
    Cgdmax  Maximum gate to drain capacitance.
    Cgdmin   Minimum gate to drain capacitance.
    Cgs       Gate to source capacitance.
    Cjo        Parasitic diode capacitance.
    Is          Parasitic diode saturation current.
    Rb         Body diode resistance.

    Therefore an example template MOSFET model is

     .model XXXX VDMOS(Rg= Rd=5 Rs=1 Vto= Kp= Cgdmax= Cgdmin= Cgs= Cjo= Is= Rb= )

  • 0 in reply to Steve Schoenbauer
    TI__Mastermind 41310 points

    Steve,

    Actually, LTSpice provides a fitting "tool" that you provide operating information from the datasheet and it "fits" the VDMOS model to the data provided. The model produced will always converge in LTSpice, but it is not very accurate for complex FET structures.

    You are more than welcome to use this tool to create models for any devices from their datasheet information. Please take a look at the accuracy that it provides based on the datasheet information though.

    I have been looking for a contact for you and believe that I have found one. He should be contacting you shortly about your needs.

    Sorry for the delay. Hard to get emails over the weekend...