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questions on TPS50601-SP design/simulation

Erik Laurila
Prodigy 180 points

Other Parts Discussed in Thread: TPS50601-SP

1.  I've been using WebBENCH to evaluate some options.  Why is the input capacitance divided between Cin and Cinx?  Is it to show there are different types of capacitors being used?


2.  I'm setting up the PSpice AC simulation using the project I downloaded from the webiste.  On the capacitors, it shows a parameter X for the Input and Output capacitors?  What is this parameter used for?


Thanks,

Erik

  • 0
    TI__Mastermind 41310 points

    Erik,

    For question 2, the X is a number of capacitors in parallel that you can use. The X is for multiples of the device value specified. In the default case, there is 1 330uF capacitor with ESR of 6mOhm. If you wanted to do several smaller caps, you could do that with this subcircuit model. It is simply there to give you some flexibility with the circuit.

    I am not certain about question 1, however, based on the datasheet information, I do not think that it is to use two different types of capacitor, but rather to reduce the input ripple to the device. The devices in parallel will have a lower overall ESR than a single device of the higher value. The design guidelines in the datasheet use two devices in parallel. The datasheet also states in some cases additional bulk capacitance may be required for the PVIN pin.

  • 0 in reply to Britt Brooks - Online Design Tools
    Prodigy 180 points
    #2: so you specify the ESR of a single cap, but can model multiple identical caps in parallel using the X parameter?

    #1: I only asked because WebBENCH generated a schematic where Cin was a polarized cap and Cinx (parallel to Cin) was a non-polarized cap.
  • 0 in reply to Erik Laurila
    TI__Mastermind 41310 points

    Erik,

    #2 - Yes. The model is set up to add the parallel capacitances and 1/R sum the ESR value. Think of it as a multiplier for multiple instances of a single capacitor model with ESR.

    #1 - Interesting. I may have missed that. In the quick example I looked at, both were non-polarized... as in the datasheet example. I guess that both reasons could be explanations and the Circuit Calculator is smart enough to cover both requirements.

    I can do some further checking into the use of the TPS50601-SP. I'll let you know if I find out any further information. Thanks for pointing that out...

  • 0 in reply to Britt Brooks - Online Design Tools
    TI__Mastermind 41310 points

    Erik,

    I talked to the designer that made the EVM for the device and supports the applications for the device. He stated that the WEBENCH® design is the design for PVIN tied to VIN and that the two capacitors CIN and CINX could be used for separate VIN and PVIN connections as well. He did add the following cautions for the device:

    Pvin pin (pins 6 and 7)  this is the drain connection for high side MOSFET.   One wants to ensure  in order to minimize inductance and  energy is coming from the localized capacitors. It is important to place these capacitors close to the drain of High side MOSFET. Otherwise it will result in higher inductance and potentially kill the part due to higher voltage spike/ stress. Most experienced customers are aware of these issues. However someone who is just getting into it may not be aware of it.

     

    Layout is a critical portion of the design,  Even if we have an excellent design and layout is not done right the part will not work.   Thus to emphasize that criticality the reason why we have input capacitors close to drain pin of high side MOSFET as I had done on the EVM that is released on the web.

    Customer needs to read the datasheet and understand that  layout and component placement on the layout is also a critical portion of the design.

    TI website has gerbers for the TPS50601-SP mini POL reference design that the customer can download and use as a guideline.


    I hope this information helps and answers your question.