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TPS53513 (but more general) Webench MLCC capacitor DC bias issues

Bruce Lott
Prodigy 220 points
Other Parts Discussed in Thread: TPS53513

A Webench design for a 9.5-16.0v input to 5.0v output @ 8A  regulator using the TPS53513 suggests MLCC cap parts that have terrible DC bias problems.  The 47uF input caps (TDK C3216X5R1E476M160AC) under 12V DC bias each have <6uF capacitance!  The 47uF output caps (Murata GRM31CR61A476KE15L) under 5V DC bias each have only 20uF capacitance (15uF at -40/+85C).  Note that these are from the manufacturer's part-specific plots/tools at low (<0.1V) AC ripple voltage, which is what I expect to be the case for this design.  It is almost meaningless to list specific part numbers that have such poor correlations (at their operating points) to their nominal capacitance values.

I read in another post that Webench applies a generic derating curve to [only] the output MLCC caps, but upon checking a number of [Murata] caps of various rated voltages, dielectrics, and physical sizes [using their excellent SimSurfing tool], it is apparent that a generic correction is not useful, especially based on rated voltage.  The Murata tool showed that the biggest dependency is actually on capacitor size (bigger package volume is better).  Even knowing this, the DC bias can have a remarkable effect on the temperature characteristic, often changing the basic datasheet curve dramatically and non-intuitively, so the combined effects are hard to anticipate.  I suspect this applies to other manufacturers' parts too.  This makes for a tedious task when trying to find suitable caps, especially if trying to minimize size and cost.

Getting back to the TI issue here, can you tell me whether Webench displays MLCC cap values that are theoretical (i.e. ideal component), or does it attempt to select values or part numbers that are intended to simply be used as listed?  How would I know which are which?  For example, does Webench indeed apply the derating curve mentioned in the post I referred to, and only to output caps?

Thanks in advance for your reply.

  • 0
    TI__Guru**** 191445 points
    I am going to move this to the Webench support forum. Only they can answer details about the component selection and rating. But yes you are correct to be concerned about this. When I design using MLCC (and I use them almost exclusively) I always check the manufacturers data to ensure I have adequate capacitance for my application and make my capacitor selection and other design considerations as appropriate.
  • 0 in reply to JohnTucker
    Prodigy 220 points
    Thanks, John. Do you lean towards dealing with large package sizes to stay within, say 25% of nominal, or accept significant derating and place more caps and/or select larger nominal values? There seems to be no free lunch here, although the benefit of the low ESR/ESL may allow choice of somewhat lower filtering capacitance. Any suggestions in this regard?
  • 0 in reply to Bruce Lott
    TI__Guru**** 191445 points

    Sounds to me like you have a firm grasp of this issue.  As you say, no free lunch.  It is always a trade off between nominal capacitance, de-rated capacitance, package size, voltage rating and number of capacitors used.  Most of my designs tend to be low voltage output less than 3.3 V, so using 10 V or 16 V rated capacitors usually results in de-rated capacitance > 70 % of nominal.  As you may have noticed in Sim Surfing, some capacitors actually increase in de-rated capacitance at 10 to 20% of rated voltage.  The reference designs I make are usually "market driven" with somewhat flexible performance requirements, so I am usually striking a balance among the above factors.  But generally speaking, I tend to go for "higher voltage rating relative to output voltage" to drive my designs.

  • 0 in reply to JohnTucker
    Prodigy 220 points
    I appreciate your input on this topic. I'm not sure how many engineers are aware of this, if they aren't focused on power supply design (I wasn't until a few weeks ago). You can mark this "answered" if it will still leave the question you tossed over to Webench open.

    Thanks again! (from a fellow amateur astronomer--noticed the Dob)
  • 0 in reply to Bruce Lott
    TI__Guru**** 191445 points
    Lets leave this open as your real question is about how and why webench selects capacitors. Thanks for you comment about the Dob. Not many know what it is. No substitute for aperture...
  • 0 in reply to JohnTucker
    TI__Expert 3085 points

    Bruce,

    Thanks for posting your question. We are looking at it and we will respond soon on this.

    Regards,

    Surinder

  • 0 in reply to Surinder Singh
    TI__Intellectual 2510 points

    Dear Bruce,

    Thanks for bringing this issue to our attention. Within the WEBENCH tools we apply derating to the output capacitor if they are ceramic. This derating was applied to the two capacitors you mentioned, but it was not as strong as that indicated on the manufacturer’s site.

    We updated the capacitance derating model for the two capacitors (GRM31CR61A476KE15L and C3216X5R1E476M160AC) and the effective capacitance now matches what is calculated by the capacitor vendor’s tool. We will let you know when the change is on production. We will work to update the rest of the capacitors in our database, although that may take some time to complete.

    Thanks for using WEBENCH and giving this feedback. Let us know if you have any more questions.

    Regards,

    Flora

  • 0 in reply to Flora Carreto
    TI__Mastermind 24700 points
    Bruce,

    To add to what Flora has mentioned, we also need to update the capacitor selection algorithm to ensure the derated capacitance is sufficient for the design. At this point, you might need to change the capacitor(s) to one's with higher voltage rating or manually check if the derated capacitance (from manufacturer tools) is sufficient for your design requirements. We are sorry for the inconvenience this might cause. Thanks for bringing up this issue.

    Regards,
    Amod
  • 0 in reply to Amod Vaze
    Prodigy 220 points

    Amod,

    Thanks for your and Flora's replies.  I appreciate that you are working on these improvements to Webench.  In the meantime, though, can you tell me how to determine the ideal design capacitances for Cin and Cout (i.e. before any adjustments for specific parts)?   I pasted your 17-May-2016 response to someone else asking about this issue below the "=====".  You also mentioned in a 12-Nov-2015 response that only Cout is presently being derated by Webench,  Is this information still accurate for Webench today (as available to non-TI personnel)?  Also, what did you mean by "We also add margin..."?  Is this an additional correction, or were you just clarifying how the graph is used to select a part with a voltage ratio that will result in an "acceptable" loss of capacitance?

    If the information is still accurate and there is no additional correction, then it would seem that I should simply divide the Webench Cout value(s) by the derating factor from the graph (knowing the voltage ratio from the Webench design), and leave the Cin value(s) as is.  I could then choose appropriate parts to try to achieve these ideal values in practice.  Am I missing anything?

    Thanks,

    Bruce

    =============================

    WEBENCH uses a generic derating curve (attached image) for output ceramic caps. The x-axis is the ratio of applied voltage to the output ceramic cap to the voltage rating of the cap and y-axis is the ratio of the actual cap value to the standard or ideal value. We also add margin on the voltage rating while selecting the caps in order to avoid too much loss of capacitor value when the voltage is applied.

    Regards,

    Amod

  • 0 in reply to Bruce Lott
    TI__Guru**** 191445 points
    For TPS53513, the minimum and maximum output capacitance is given in Table 3. It is specifically for X5R, 1206, 10 V capacitors, so it takes the DC bias effect into account. As you will notice the minimum capacitance varies quite a lot with output voltage. The maximum is stated to be 30 x 100 uF. I doubt that anyone would ever use that much.

    In general, the capacitance range is based on placing FLC such that Fco falls in a range that allows the circuit to be stable. DCAP3 is inherently stable, but very low Cout can result in a high enough FLC that forces Fco above Fsw/4.

    The other considerations for Cout are output voltage ripple attenuation and transient response. For ceramic output capacitors, the ESR is very low so ripple is generally not a n issue. the main feature of DCAP type control is fast transient response with minimal output capacitance, so that is not usually a major driver either unless you need very low undershoot and overshoot during load step changes.
  • 0 in reply to Bruce Lott
    TI__Mastermind 24700 points
    Bruce,

    You are right. The derating factor currently applies only to the output capacitor chosen. So, you get the ideal capacitor value, let's say 47uF for the GRM31CR61A476KE15L cap chosen at the output. Since you are using 5V at the output and the cap VDC rating is 10V, the current WEBENCH derated value is about 85% from the graph above. Of course, the model is turning out to be optimistic whereas the manufacturer is mentioning that you'll actually only get about 20uF on the 47uF (~42% value).

    The "margin" concept is where when we calculate the cap value based on requirements like voltage ripple, voltage deviation during load transient, etc. , we do not just use that value for picking the cap directly. But, instead, we add a margin on top of that. So, for example, based on the design requirements, let's say we calculate a value of ~77uF, we increase it further and that typically is about 40% more. So, you get about 110uF for this design. You can look at the target/lowerbound/upperbound for the output cap by clicking on the "BOM" tab and then clicking "select alternate part". Above the list of capacitors, you will see limits for capacitance, voltage rating, Irms values, etc. which are used to actually pick a capacitor. But, as mentioned, the absolute strictly needed value is lower than the lowerbound we use. This tries to ensure you have enough cap in case the voltage derating from the curve above does not match up the real manufacturer data like you pointed out.

    Hope this helps. I also see some cool design comments from John which will help pick a good capacitor.

    Regards,
    Amod
  • 0 in reply to JohnTucker
    Prodigy 220 points
    Thanks, John. I actually was reviewing a design by another engineer who was relying heavily on Webench, and haven't had a chance to dig far into the data sheet yet. I appreciate your detailed comments, and will use them in conjunction with the datasheet to help refine the design.
  • 0 in reply to Amod Vaze
    Prodigy 220 points
    Amod,

    Thanks for providing more detail about how the values and components are selected in Webench. I'm still not sure about where the line is between suggesting values (with bounds), and factoring in component derating. It's clear from your explanation that the target and lower bounds already have a (typically 40%) margin above what the design would absolutely require. Is the upper bound margined up as well, or is that not to be exceeded? Also, is the DC bias derating taken into account when building the alternate component table, or is it already included in the displayed target and lower bound?
  • 0 in reply to Bruce Lott
    TI__Mastermind 24700 points

    Bruce,

    The upperbound typically is not a hard stop on the cap value but we do account for a specific range if it is mentioned in the datasheet as is the case for some types of device architectures.

    The DC bias derating is not included in the target/lowerbound values. It still needs to be accounted for in the alternate component table where in we would not show the capacitors which have a derated value lower than the lowerbound requirement . This would also be part of what I was referring to in the message from before - "we also need to update the capacitor selection algorithm to ensure the derated capacitance is sufficient for the design."

    Regards,

    Amod

  • 0 in reply to Amod Vaze
    Prodigy 220 points

    Thanks to you and John for your respective answers in the Webench and TPS53513 areas! I marked your final replies as Answers, and I'll post if I run into further questions or problems.