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TPS43061 - About simulation at VIN=5V, VOUT=24V, IOUT=5A
The reason for the design not being created is that a suitable FET could not be found for these input, output conditions.
The reason is because the high currents through the FET cause an increase in temperature causing their Junction temperature (Tj) to be higher than that could be supported by the FET. The Tj max of the FETs has a derating of 1.25 (so we allow the 150deg FET to operate at a max Tj of only 120 degC).
You could try increasing the Vinmin to 6.5V and you can see a design being created with the TPS43061. You could try creating a design at 6V Vinmin with the TPS43060.
