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PCN communication about WeBench

Vincenzo Pizzolante
Mastermind 25296 points
Other Parts Discussed in Thread: TPS54320

hi all,

some customers of mine received the following communication from the Webench team:

This is to inform you that one or more of Texas Instruments’ WEBENCH® power designs may have incorrect operating values. Due to a bug in the calculations either the recommended junction temperature limits were violated, or the MOSFET selection was in error, and your design could have been unstable. We have corrected these bugs and implemented more rigorous checks. The following design(s) were identified as possibly being affected by this bug: (list of all affected simulations follow. The TPS54320 is included).

Can you please tell me what has been changed in the model, in particular for the TPS54320, that generates the mail above?

thanks a lot in advance

KR

Vincenzo

  • 0
    TI__Genius 17905 points
    Hi Vincenzo,

    I just sent you an email requesting a little more information that will help me address the question on the TPS54320 properly.

    I'll post any specific conclusions from that offline discussion back here later.

    Regards,
    Kris
  • 0 in reply to Kris F
    TI__Genius 17905 points
    Vincenzo, Thanks for the info. I'm sharing parts of our email correspondence here:

    The TPS54320 designs were reported due to improvements to the peak current mode (PCM) loop model in WEBENCH. PCM control should show voltage-mode-like behavior when slope compensation is high for certain operating conditions. Our model was not capturing this behavior and the compensation was thus not designed to give adequate phase margin for the customer’s design conditions. We improved the model to account for this behavior, so updating or recreating the design in WEBENCH per the notification’s instructions will show correct results.

    The other designs were reported for potential IC and MOSFET junction temperature issues. WEBENCH performs a number of design checks to determine if a design is safe, one of which is a check of calculated junction temperature against allowed limits. In the past, temperature checks were only done at max Vin for buck (min Vin for boost). This is often a good assumption, however, the worst case temperatures can actually occur at the opposite end of the Vin range, min Vin for a buck. We added more robust design checks in WEBENCH to address this and determined which past designs may have exceeded temperature limits. There were also some issues in external FET temperature calculations that were causing inaccurate FET temperatures to be reported in the GUI. These issues have been fixed, and updating or recreating the design in WEBENCH per the notification’s instructions will show correct results.

    Best regards,
    Kris