dear, I use the model downloaded from TI website to simulate ucc28600, but it can't converge.
the error discription:
**** 03/29/17 10:25:11 ***** PSpice 16.6.0 (October 2012) ***** ID# 0 ********
** Profile: "SCHEMATIC1-TAPPED_TRANSFORMER" [ E:\zhuxuefeng\Pspice\project\ucc28600-pspicefiles\schematic1\tapped_transformer.sim ]
**** CIRCUIT DESCRIPTION
******************************************************************************
** Creating circuit file "TAPPED_TRANSFORMER.cir"
** WARNING: THIS AUTOMATICALLY GENERATED FILE MAY BE OVERWRITTEN BY SUBSEQUENT SIMULATIONS
*Libraries:
* Profile Libraries :
* Local Libraries :
* From [PSPICE NETLIST] section of E:\SPB_Data\cdssetup\OrCAD_PSpice/16.6.0/PSpice.ini file:
.lib "E:\zhuxuefeng\Pspice\project\LM431_TRANS.LIB"
.lib "E:\zhuxuefeng\Pspice\project\ucc28600.lib"
.lib "E:\zhuxuefeng\Pspice\xiaomi_singleline\OPA2330_PSPICE_AIO\opa2330.lib"
.lib "E:\zhuxuefeng\Pspice\xiaomi_singleline\TLC555_PSPICE_AIO\tlc555.lib"
.lib "C:\Cadence\SPB_16.6\tools\capture\library\pspice\zhuxuefeng\zhuxuefeng.lib"
.lib "E:\zhuxuefeng\Pspice\BASSOBOOK\OrCAD\Libraries\application.lib"
.lib "nom.lib"
*Analysis directives:
.TRAN 0 50M 0 20n SKIPBP
.OPTIONS PREORDER
.OPTIONS ADVCONV
.OPTIONS ABSTOL= 1E-08
.OPTIONS GMIN= 1.0E-11
.OPTIONS ITL1= 1000
.OPTIONS ITL2= 2000
.OPTIONS ITL4= 1500
.OPTIONS RELTOL= 0.002
.OPTIONS VNTOL= 1E-05
.PROBE64 V(alias(*)) I(alias(*)) W(alias(*)) D(alias(*)) NOISE(alias(*))
.INC "..\SCHEMATIC1.net"
**** INCLUDING SCHEMATIC1.net ****
* source UCC28600
L_L1 N01151 N02817 820u
L_L2 N03170 N03190 4.85u
Kn_K1 L_L1 L_L2
+ L_L3 1
R_R4 0 N10440 0.5 TC=0,0
C_C2 N03926 0 12u
R_R7 N12459 N02981 100 TC=0,0
R_R8 N02981 N02767 82k TC=0,0
C_C3 N02981 N02767 1n TC=0,0
D_D2 N03170 N03174 1N5820
R_R9 0 N03174 0.3 TC=0,0
R_R10 0 N03863 20k TC=0,0
R_R11 N03863 N11467 110k TC=0,0
X_U2 N05339 0 N05245 LM431_TRANS
R_R14 N05245 N03174 180k TC=0,0
R_R15 0 N05245 47k TC=0,0
C_C5 N05245 N05339 47n TC=0,0
R_R16 N05339 N03174 20k TC=0,0
R_R18 N02817 N02767 1 TC=0,0
R_R19 N02767 N02746 0.5 TC=0,0
R_R20 0 N03190 1 TC=0,0
Q_Q1 N06585 N05339 N06669 DH3468CN
Q_Q2 N06585 N06585 0 Q40242
Q_Q3 N08836 N06585 0 Q40242
R_R22 N06669 N03174 20k TC=0,0
C_C6 N02767 0 47u
V_V1 N02746 0 400Vdc
C_C7 N03174 0 2200u
R_R23 N07812 N10947 100 TC=0,0
R_R24 N10440 N10436 1.1k TC=0,0
L_L3 N14017 0 6u
D_D3 N11467 N03926 1N5820
R_R25 N03926 N02767 500k TC=0,0
D_D4 N01151 N12459 1N5820
Q_Q4 N01151 N07812 N10440 Q40242
X_U3 N12935 N08836 N10436 0 N10947 N03926 N03863 N12931 UCC28600_0
C_C8 0 N12935 1n TC=0,0
R_R26 N14017 N11467 1 TC=0,0
**** RESUMING TAPPED_TRANSFORMER.cir ****
.END
**** Generated AtoD and DtoA Interfaces ****
*
* Analog/Digital interface for node X_U3.7
*
* Moving X_U3.XU1.U14:OUT1 from analog node X_U3.7 to new digital node X_U3.7$DtoA
X$X_U3.7_DtoA1
+ X_U3.7$DtoA
+ X_U3.7
+ X_U3.REF
+ 0
+ DtoA_STD
+ PARAMS: DRVH= 96.4 DRVL= 104 CAPACITANCE= 0
*
* Analog/Digital interface for node X_U3.REF
*
* Moving X_U3.XU1.U10:D1 from analog node X_U3.REF to new digital node X_U3.REF$AtoD
X$X_U3.REF_AtoD1
+ X_U3.REF
+ X_U3.REF$AtoD
+ X_U3.REF
+ 0
+ AtoD_STD
+ PARAMS: CAPACITANCE= 0
* Moving X_U3.XU1.U10:PREBAR from analog node X_U3.REF to new digital node X_U3.REF$AtoD2
X$X_U3.REF_AtoD2
+ X_U3.REF
+ X_U3.REF$AtoD2
+ X_U3.REF
+ 0
+ AtoD_STD
+ PARAMS: CAPACITANCE= 0
* Moving X_U3.XU1.U15:IN1 from analog node X_U3.REF to new digital node X_U3.REF$AtoD3
X$X_U3.REF_AtoD3
+ X_U3.REF
+ X_U3.REF$AtoD3
+ X_U3.REF
+ 0
+ AtoD_STD
+ PARAMS: CAPACITANCE= 0
* Moving X_U3.XU1.U16:IN1 from analog node X_U3.REF to new digital node X_U3.REF$AtoD4
X$X_U3.REF_AtoD4
+ X_U3.REF
+ X_U3.REF$AtoD4
+ X_U3.REF
+ 0
+ AtoD_LS
+ PARAMS: CAPACITANCE= 0
* Moving X_U3.XU14.U5:CLRBAR from analog node X_U3.REF to new digital node X_U3.REF$AtoD5
X$X_U3.REF_AtoD5
+ X_U3.REF
+ X_U3.REF$AtoD5
+ X_U3.REF
+ 0
+ AtoD_S
+ PARAMS: CAPACITANCE= 0
* Moving X_U3.XU14.U10:PREBAR from analog node X_U3.REF to new digital node X_U3.REF$AtoD6
X$X_U3.REF_AtoD6
+ X_U3.REF
+ X_U3.REF$AtoD6
+ X_U3.REF
+ 0
+ AtoD_S
+ PARAMS: CAPACITANCE= 0
* Moving X_U3.XU14.U11:PREBAR from analog node X_U3.REF to new digital node X_U3.REF$AtoD7
X$X_U3.REF_AtoD7
+ X_U3.REF
+ X_U3.REF$AtoD7
+ X_U3.REF
+ 0
+ AtoD_STD
+ PARAMS: CAPACITANCE= 0
* Moving X_U3.U4:IN1 from analog node X_U3.REF to new digital node X_U3.REF$AtoD8
X$X_U3.REF_AtoD8
+ X_U3.REF
+ X_U3.REF$AtoD8
+ X_U3.REF
+ 0
+ AtoD_STD
+ PARAMS: CAPACITANCE= 0
* Moving X_U3.U10:D1 from analog node X_U3.REF to new digital node X_U3.REF$AtoD9
X$X_U3.REF_AtoD9
+ X_U3.REF
+ X_U3.REF$AtoD9
+ X_U3.REF
+ 0
+ AtoD_S
+ PARAMS: CAPACITANCE= 0
* Moving X_U3.U10:PREBAR from analog node X_U3.REF to new digital node X_U3.REF$AtoD10
X$X_U3.REF_AtoD10
+ X_U3.REF
+ X_U3.REF$AtoD10
+ X_U3.REF
+ 0
+ AtoD_S
+ PARAMS: CAPACITANCE= 0
*
* Analog/Digital interface for node X_U3.OUT_
*
* Moving X_U3.XU14.U1:IN2 from analog node X_U3.OUT_ to new digital node X_U3.OUT_$AtoD
X$X_U3.OUT__AtoD1
+ X_U3.OUT_
+ X_U3.OUT_$AtoD
+ X_U3.REF
+ 0
+ AtoD_STD
+ PARAMS: CAPACITANCE= 0
* Moving X_U3.U10:QBAR1 from analog node X_U3.OUT_ to new digital node X_U3.OUT_$DtoA
X$X_U3.OUT__DtoA1
+ X_U3.OUT_$DtoA
+ X_U3.OUT_
+ X_U3.REF
+ 0
+ DtoA_S
+ PARAMS: DRVH= 72.7 DRVL= 60.6 CAPACITANCE= 0
*
* Analog/Digital interface for node X_U3.9
*
* Moving X_U3.U10:Q1 from analog node X_U3.9 to new digital node X_U3.9$DtoA
X$X_U3.9_DtoA1
+ X_U3.9$DtoA
+ X_U3.9
+ X_U3.REF
+ 0
+ DtoA_S
+ PARAMS: DRVH= 72.7 DRVL= 60.6 CAPACITANCE= 0
*
* Analog/Digital interface for node X_U3.10
*
* Moving X_U3.U12:IN1 from analog node X_U3.10 to new digital node X_U3.10$AtoD
X$X_U3.10_AtoD1
+ X_U3.10
+ X_U3.10$AtoD
+ X_U3.REF
+ 0
+ AtoD_4000A
+ PARAMS: CAPACITANCE= 0
*
* Analog/Digital interface for node X_U3.11
*
* Moving X_U3.U12:IN2 from analog node X_U3.11 to new digital node X_U3.11$AtoD
X$X_U3.11_AtoD1
+ X_U3.11
+ X_U3.11$AtoD
+ X_U3.REF
+ 0
+ AtoD_4000A
+ PARAMS: CAPACITANCE= 0
*
* Analog/Digital interface for node X_U3.12
*
* Moving X_U3.U12:IN3 from analog node X_U3.12 to new digital node X_U3.12$AtoD
X$X_U3.12_AtoD1
+ X_U3.12
+ X_U3.12$AtoD
+ X_U3.REF
+ 0
+ AtoD_4000A
+ PARAMS: CAPACITANCE= 0
*
* Analog/Digital interface for node X_U3.SS_OVR
*
* Moving X_U3.XU1.U2:IN2 from analog node X_U3.SS_OVR to new digital node X_U3.SS_OVR$AtoD
X$X_U3.SS_OVR_AtoD1
+ X_U3.SS_OVR
+ X_U3.SS_OVR$AtoD
+ X_U3.REF
+ 0
+ AtoD_STD
+ PARAMS: CAPACITANCE= 0
* Moving X_U3.XU2.U11:IN1 from analog node X_U3.SS_OVR to new digital node X_U3.SS_OVR$AtoD2
X$X_U3.SS_OVR_AtoD2
+ X_U3.SS_OVR
+ X_U3.SS_OVR$AtoD2
+ X_U3.XU2.PWR
+ 0
+ AtoD_STD
+ PARAMS: CAPACITANCE= 0
*
* Analog/Digital interface for node X_U3.35
*
* Moving X_U3.U3:IN1 from analog node X_U3.35 to new digital node X_U3.35$AtoD
X$X_U3.35_AtoD1
+ X_U3.35
+ X_U3.35$AtoD
+ X_U3.REF
+ 0
+ AtoD_STD
+ PARAMS: CAPACITANCE= 0
*
* Analog/Digital interface for node X_U3.BURST
*
* Moving X_U3.XU1.U2:IN1 from analog node X_U3.BURST to new digital node X_U3.BURST$AtoD
X$X_U3.BURST_AtoD1
+ X_U3.BURST
+ X_U3.BURST$AtoD
+ X_U3.REF
+ 0
+ AtoD_STD
+ PARAMS: CAPACITANCE= 0
*
* Analog/Digital interface for node X_U3.XU14.60
*
* Moving X_U3.XU14.U19:IN1 from analog node X_U3.XU14.60 to new digital node X_U3.XU14.60$AtoD
X$X_U3.XU14.60_AtoD1
+ X_U3.XU14.60
+ X_U3.XU14.60$AtoD
+ X_U3.REF
+ 0
+ AtoD_STD
+ PARAMS: CAPACITANCE= 0
*
* Analog/Digital interface for node X_U3.XU14.61
*
* Moving X_U3.XU14.U18:OUT1 from analog node X_U3.XU14.61 to new digital node X_U3.XU14.61$DtoA
X$X_U3.XU14.61_DtoA1
+ X_U3.XU14.61$DtoA
+ X_U3.XU14.61
+ X_U3.REF
+ 0
+ DtoA_STD
+ PARAMS: DRVH= 96.4 DRVL= 104 CAPACITANCE= 0
*
* Analog/Digital interface for node X_U3.XU14.56
*
* Moving X_U3.XU14.U17:IN1 from analog node X_U3.XU14.56 to new digital node X_U3.XU14.56$AtoD
X$X_U3.XU14.56_AtoD1
+ X_U3.XU14.56
+ X_U3.XU14.56$AtoD
+ X_U3.REF
+ 0
+ AtoD_S
+ PARAMS: CAPACITANCE= 0
* Moving X_U3.XU14.U18:IN1 from analog node X_U3.XU14.56 to new digital node X_U3.XU14.56$AtoD2
X$X_U3.XU14.56_AtoD2
+ X_U3.XU14.56
+ X_U3.XU14.56$AtoD2
+ X_U3.REF
+ 0
+ AtoD_STD
+ PARAMS: CAPACITANCE= 0
* Moving X_U3.XU14.U20:IN2 from analog node X_U3.XU14.56 to new digital node X_U3.XU14.56$AtoD3
X$X_U3.XU14.56_AtoD3
+ X_U3.XU14.56
+ X_U3.XU14.56$AtoD3
+ X_U3.REF
+ 0
+ AtoD_S
+ PARAMS: CAPACITANCE= 0
* Moving X_U3.XU14.U10:CLRBAR from analog node X_U3.XU14.56 to new digital node X_U3.XU14.56$AtoD4
X$X_U3.XU14.56_AtoD4
+ X_U3.XU14.56
+ X_U3.XU14.56$AtoD4
+ X_U3.REF
+ 0
+ AtoD_S
+ PARAMS: CAPACITANCE= 0
* Moving X_U3.XU14.U11:CLRBAR from analog node X_U3.XU14.56 to new digital node X_U3.XU14.56$AtoD5
X$X_U3.XU14.56_AtoD5
+ X_U3.XU14.56
+ X_U3.XU14.56$AtoD5
+ X_U3.REF
+ 0
+ AtoD_STD
+ PARAMS: CAPACITANCE= 0
*
* Analog/Digital interface for node X_U3.Q
*
* Moving X_U3.XU2.U1:IN2 from analog node X_U3.Q to new digital node X_U3.Q$AtoD
X$X_U3.Q_AtoD1
+ X_U3.Q
+ X_U3.Q$AtoD
+ X_U3.XU2.PWR
+ 0
+ AtoD_S
+ PARAMS: CAPACITANCE= 0
* Moving X_U3.U10:CLK from analog node X_U3.Q to new digital node X_U3.Q$AtoD2
X$X_U3.Q_AtoD2
+ X_U3.Q
+ X_U3.Q$AtoD2
+ X_U3.REF
+ 0
+ AtoD_S
+ PARAMS: CAPACITANCE= 0
* Moving X_U3.XU2.U3:OUT1 from analog node X_U3.Q to new digital node X_U3.Q$DtoA
X$X_U3.Q_DtoA1
+ X_U3.Q$DtoA
+ X_U3.Q
+ X_U3.XU2.PWR
+ 0
+ DtoA_S
+ PARAMS: DRVH= 72.7 DRVL= 60.6 CAPACITANCE= 0
*
* Analog/Digital interface for node X_U3.XU14.42
*
* Moving X_U3.XU14.U7:IN1 from analog node X_U3.XU14.42 to new digital node X_U3.XU14.42$AtoD
X$X_U3.XU14.42_AtoD1
+ X_U3.XU14.42
+ X_U3.XU14.42$AtoD
+ X_U3.REF
+ 0
+ AtoD_S
+ PARAMS: CAPACITANCE= 0
*
* Analog/Digital interface for node X_U3.LINE_OVP
*
* Moving X_U3.XU1.U4:IN2 from analog node X_U3.LINE_OVP to new digital node X_U3.LINE_OVP$AtoD
X$X_U3.LINE_OVP_AtoD1
+ X_U3.LINE_OVP
+ X_U3.LINE_OVP$AtoD
+ X_U3.REF
+ 0
+ AtoD_STD
+ PARAMS: CAPACITANCE= 0
*
* Analog/Digital interface for node X_U3.LOAD_OVP
*
* Moving X_U3.XU1.U3:IN1 from analog node X_U3.LOAD_OVP to new digital node X_U3.LOAD_OVP$AtoD
X$X_U3.LOAD_OVP_AtoD1
+ X_U3.LOAD_OVP
+ X_U3.LOAD_OVP$AtoD
+ X_U3.REF
+ 0
+ AtoD_STD
+ PARAMS: CAPACITANCE= 0
*
* Analog/Digital interface for node X_U3.XU2.80
*
* Moving X_U3.XU2.U2:IN1 from analog node X_U3.XU2.80 to new digital node X_U3.XU2.80$AtoD
X$X_U3.XU2.80_AtoD1
+ X_U3.XU2.80
+ X_U3.XU2.80$AtoD
+ X_U3.XU2.PWR
+ 0
+ AtoD_STD
+ PARAMS: CAPACITANCE= 0
*
* Analog/Digital interface for node X_U3.CLK_130K
*
* Moving X_U3.XU2.U5:IN3 from analog node X_U3.CLK_130K to new digital node X_U3.CLK_130K$AtoD
X$X_U3.CLK_130K_AtoD1
+ X_U3.CLK_130K
+ X_U3.CLK_130K$AtoD
+ X_U3.XU2.PWR
+ 0
+ AtoD_STD
+ PARAMS: CAPACITANCE= 0
* Moving X_U3.XU14.U12:IN1 from analog node X_U3.CLK_130K to new digital node X_U3.CLK_130K$AtoD2
X$X_U3.CLK_130K_AtoD2
+ X_U3.CLK_130K
+ X_U3.CLK_130K$AtoD2
+ X_U3.REF
+ 0
+ AtoD_S
+ PARAMS: CAPACITANCE= 0
*
* Analog/Digital interface for node X_U3.XU2.82
*
* Moving X_U3.XU2.U10:IN2 from analog node X_U3.XU2.82 to new digital node X_U3.XU2.82$AtoD
X$X_U3.XU2.82_AtoD1
+ X_U3.XU2.82
+ X_U3.XU2.82$AtoD
+ X_U3.XU2.PWR
+ 0
+ AtoD_S
+ PARAMS: CAPACITANCE= 0
*
* Analog/Digital interface for node X_U3.XU1.92
*
* Moving X_U3.XU1.U3:IN2 from analog node X_U3.XU1.92 to new digital node X_U3.XU1.92$AtoD
X$X_U3.XU1.92_AtoD1
+ X_U3.XU1.92
+ X_U3.XU1.92$AtoD
+ X_U3.REF
+ 0
+ AtoD_STD
+ PARAMS: CAPACITANCE= 0
*
* Analog/Digital interface for node X_U3.XU1.95
*
* Moving X_U3.XU1.U17:IN2 from analog node X_U3.XU1.95 to new digital node X_U3.XU1.95$AtoD
X$X_U3.XU1.95_AtoD1
+ X_U3.XU1.95
+ X_U3.XU1.95$AtoD
+ X_U3.REF
+ 0
+ AtoD_STD
+ PARAMS: CAPACITANCE= 0
* Moving X_U3.XU1.U12:IN1 from analog node X_U3.XU1.95 to new digital node X_U3.XU1.95$AtoD2
X$X_U3.XU1.95_AtoD2
+ X_U3.XU1.95
+ X_U3.XU1.95$AtoD2
+ X_U3.REF
+ 0
+ AtoD_STD
+ PARAMS: CAPACITANCE= 0
*
* Analog/Digital interface for node X_U3.XU1.97
*
* Moving X_U3.XU1.U2:OUT1 from analog node X_U3.XU1.97 to new digital node X_U3.XU1.97$DtoA
X$X_U3.XU1.97_DtoA1
+ X_U3.XU1.97$DtoA
+ X_U3.XU1.97
+ X_U3.REF
+ 0
+ DtoA_STD
+ PARAMS: DRVH= 96.4 DRVL= 104 CAPACITANCE= 0
*
* Analog/Digital interface power supply subcircuits
*
X$CD4000_PWR 0 CD4000_PWR
X$DIGIFPWR 0 DIGIFPWR
**** 03/29/17 10:25:11 ***** PSpice 16.6.0 (October 2012) ***** ID# 0 ********
** Profile: "SCHEMATIC1-TAPPED_TRANSFORMER" [ E:\zhuxuefeng\Pspice\project\ucc28600-pspicefiles\schematic1\tapped_transformer.sim ]
**** Diode MODEL PARAMETERS
******************************************************************************
1N5820 D74CLMP D74 D74SCLMP
IS 1.000000E-03 1.000000E-15 100.000000E-18 10.000000E-12
N 2.34208
BV 20
IBV 2.000000E-03
RS .027467 2 25 2
CJO 636.939000E-12 2.000000E-12 2.000000E-12 2.000000E-12
VJ 1.5 .7
M .364419
EG .550905
XTI 3.02706
D74S
IS 1.000000E-12
RS 25
CJO 2.000000E-12
VJ .7
**** 03/29/17 10:25:11 ***** PSpice 16.6.0 (October 2012) ***** ID# 0 ********
** Profile: "SCHEMATIC1-TAPPED_TRANSFORMER" [ E:\zhuxuefeng\Pspice\project\ucc28600-pspicefiles\schematic1\tapped_transformer.sim ]
**** BJT MODEL PARAMETERS
******************************************************************************
DH3468CN Q40242 Q74 Q74S
PNP NPN NPN NPN
LEVEL 1 1 1 1
IS 336.700000E-15 69.280000E-18 100.000000E-18 100.000000E-18
BF 73.94 285.6 49 49
NF 1 1 1 1
VAF 100 100
IKF .6 .02229
ISE 69.280000E-18 100.000000E-18 100.000000E-18
NE 1.183
BR .3082 1.153 .03 .33
NR 1 1 1 1
ISC 400.000000E-18 400.000000E-18
ISS 0 0 0 0
RB 10 10 50 50
RE 0 0 0 0
RC .5 4 20 20
CJE 87.820000E-12 939.800000E-15 1.000000E-12 1.000000E-12
VJE .75 .75 .9 .9
MJE .3551 .3453 .5 .5
CJC 39.630000E-12 893.100000E-15 500.000000E-15 500.000000E-15
VJC .75 .75 .8 .8
MJC .3357 .3017 .33 .33
XCJC 1 1 1 1
CJS 0 0 3.000000E-12 3.000000E-12
VJS .75 .75 .7 .7
MJS .33 .33
TF 800.000000E-12 141.100000E-12 200.000000E-12 200.000000E-12
XTF 30
VTF 10
ITF .27
TR 256.900000E-09 1.578000E-09 10.000000E-09 10.000000E-09
XTB 1.5 1.5
KF 0 0 0 0
AF 1 1 1 1
CN 2.2 2.42 2.42 2.42
D .52 .87 .87 .87
**** 03/29/17 10:25:11 ***** PSpice 16.6.0 (October 2012) ***** ID# 0 ********
** Profile: "SCHEMATIC1-TAPPED_TRANSFORMER" [ E:\zhuxuefeng\Pspice\project\ucc28600-pspicefiles\schematic1\tapped_transformer.sim ]
**** Digital Input MODEL PARAMETERS
******************************************************************************
DIN74 DIN74S
S0NAME 0 0
S0TSW 3.500000E-09 1.500000E-09
S0RLO 7.13 12
S0RHI 389 389
S1NAME 1 1
S1TSW 5.500000E-09 1.500000E-09
S1RLO 467 224
S1RHI 200 74.7
S2NAME X X
S2TSW 3.500000E-09 1.500000E-09
S2RLO 42.9 34.6
S2RHI 116 98.4
S3NAME R R
S3TSW 3.500000E-09 1.500000E-09
S3RLO 42.9 34.6
S3RHI 116 98.4
S4NAME F F
S4TSW 3.500000E-09 1.500000E-09
S4RLO 42.9 34.6
S4RHI 116 98.4
S5NAME Z Z
S5TSW 3.500000E-09 1.500000E-09
S5RLO 200.000000E+03 200.000000E+03
S5RHI 200.000000E+03 200.000000E+03
**** 03/29/17 10:25:11 ***** PSpice 16.6.0 (October 2012) ***** ID# 0 ********
** Profile: "SCHEMATIC1-TAPPED_TRANSFORMER" [ E:\zhuxuefeng\Pspice\project\ucc28600-pspicefiles\schematic1\tapped_transformer.sim ]
**** Digital Output MODEL PARAMETERS
******************************************************************************
DO74 DO74LS DO74S DO4000A
TIMESTEP 100.000000E-12 100.000000E-12 100.000000E-12 100.000000E-12
S0NAME X X X X
S0VHI 2 2 2 .5
S0VLO .8 .8 .8 -.5
S1NAME 0 0 0 0
S1VHI .8 .8 .8 -.5
S1VLO -1.5 -1.5 -1.5 -3
S2NAME R R R R
S2VHI 1.4 1.2 1.35 .05
S2VLO .8 .8 .8 -.5
S3NAME R R R R
S3VHI 2 2 2 .5
S3VLO 1.3 1.1 1.25 -.05
S4NAME X X X X
S4VHI 2 2 2 .5
S4VLO .8 .8 .8 -.5
S5NAME 1 1 1 1
S5VHI 7 7 7 3
S5VLO 2 2 2 .5
S6NAME F F F F
S6VHI 2 2 2 .5
S6VLO 1.3 1.1 1.25 -.05
S7NAME F F F F
S7VHI 1.4 1.2 1.35 .05
S7VLO .8 .8 .8 -.5
**** 03/29/17 10:25:11 ***** PSpice 16.6.0 (October 2012) ***** ID# 0 ********
** Profile: "SCHEMATIC1-TAPPED_TRANSFORMER" [ E:\zhuxuefeng\Pspice\project\ucc28600-pspicefiles\schematic1\tapped_transformer.sim ]
**** Digital Gate MODEL PARAMETERS
******************************************************************************
X_U3.XU14.U_SN7432
TPLHMN 6.000000E-09
TPLHTY 15.000000E-09
TPLHMX 24.000000E-09
TPHLMN 8.800000E-09
TPHLTY 22.000000E-09
TPHLMX 35.200000E-09
**** 03/29/17 10:25:11 ***** PSpice 16.6.0 (October 2012) ***** ID# 0 ********
** Profile: "SCHEMATIC1-TAPPED_TRANSFORMER" [ E:\zhuxuefeng\Pspice\project\ucc28600-pspicefiles\schematic1\tapped_transformer.sim ]
**** Digital Edge Triggered FF MODEL PARAMETERS
******************************************************************************
X_U3.U_SN74AS74
TPCLKQLHMN 2.800000E-09
TPCLKQLHTY 7.000000E-09
TPCLKQLHMX 11.200000E-09
TPCLKQHLMN 3.600000E-09
TPCLKQHLTY 9.000000E-09
TPCLKQHLMX 14.400000E-09
TPPCQLHMN 0
TPPCQLHTY 0
TPPCQLHMX 0
TPPCQHLMN 0
TPPCQHLTY 0
TPPCQHLMX 0
TWCLKLMN 0
TWCLKLTY 0
TWCLKLMX 0
TWCLKHMN 0
TWCLKHTY 0
TWCLKHMX 0
TWPCLMN 0
TWPCLTY 0
TWPCLMX 0
TSUDCLKMN 0
TSUDCLKTY 0
TSUDCLKMX 0
TSUPCCLKHMN 0
TSUPCCLKHTY 0
TSUPCCLKHMX 0
THDCLKMN 0
THDCLKTY 0
THDCLKMX 0
TSUCECLKMN 0
TSUCECLKTY 0
TSUCECLKMX 0
THCECLKMN 0
THCECLKTY 0
THCECLKMX 0
**** 03/29/17 10:25:11 ***** PSpice 16.6.0 (October 2012) ***** ID# 0 ********
** Profile: "SCHEMATIC1-TAPPED_TRANSFORMER" [ E:\zhuxuefeng\Pspice\project\ucc28600-pspicefiles\schematic1\tapped_transformer.sim ]
**** Digital IO MODEL PARAMETERS
******************************************************************************
IO_4000A IO_STD IO_S IO_LS
DRVL 1.649000E+03 104 60.6 157
DRVH 1.649000E+03 96.4 72.7 108
AtoD1 AtoD_4000A AtoD_STD AtoD_S AtoD_LS
AtoD2 AtoD_4000A_NX AtoD_STD_NX AtoD_S_NX AtoD_LS_NX
AtoD3 AtoD_4000A AtoD_STD AtoD_S AtoD_LS
AtoD4 AtoD_4000A_NX AtoD_STD_NX AtoD_S_NX AtoD_LS_NX
DtoA1 DtoA_4000A DtoA_STD DtoA_S DtoA_LS
DtoA2 DtoA_4000A DtoA_STD DtoA_S DtoA_LS
DtoA3 DtoA_4000A DtoA_STD DtoA_S DtoA_LS
DtoA4 DtoA_4000A DtoA_STD DtoA_S DtoA_LS
DIGPOWER CD4000_PWR
TSWHL1 7.070000E-09 1.511000E-09 788.000000E-12 2.724000E-09
TSWHL2 6.940000E-09 1.487000E-09 795.000000E-12 2.724000E-09
TSWHL3 9.330000E-09 1.511000E-09 788.000000E-12 2.724000E-09
TSWHL4 9.180000E-09 1.487000E-09 795.000000E-12 2.724000E-09
TSWLH1 8.580000E-09 3.517000E-09 889.000000E-12 2.104000E-09
TSWLH2 8.370000E-09 3.564000E-09 887.000000E-12 2.104000E-09
TSWLH3 10.730000E-09 3.517000E-09 889.000000E-12 2.104000E-09
TSWLH4 10.590000E-09 3.564000E-09 887.000000E-12 2.104000E-09
TPWRT 100.000000E+03 100.000000E+03 100.000000E+03 100.000000E+03
IO_STM
DRVL 0
DRVH 0
DtoA1 DtoA_STM
DtoA2 DtoA_STM
DtoA3 DtoA_STM
DtoA4 DtoA_STM
TPWRT 100.000000E+03
Reducing minimum delta to make the circuit converge.
Reducing minimum delta to make the circuit converge.
Reducing minimum delta to make the circuit converge.
Reducing minimum delta to make the circuit converge.
Reducing minimum delta to make the circuit converge.
ERROR(ORPSIM-15138): Convergence problem in transient analysis at Time = 1.212E-09.
Time step = 93.13E-21, minimum allowable step size = 1.000E-18
These supply currents failed to converge:
I(X_U3.XOP3.EGND) = -1.867mA \ -1.909mA
I(X_U3.XU14.XIOP1.EO) = 169.63uA \ -2.710uA
I(X_U3.XU8.XOP3.EGND) = -1.939mA \ -1.907mA
I(X_U3.XU8.XOP2.EGND) = -260.51uA \ -218.90uA
I(X_U3.XU8.XOP1.EGND) = -180.24uA \ -222.21uA
I(L_L2) = 296.08uA \ 296.80uA
I(X_U2.V4) = -466.11uA \ -446.15uA
These devices failed to converge:
X$X_U3.REF_AtoD1.Q1 X$X_U3.REF_AtoD2.Q1 X$X_U3.REF_AtoD3.Q1
X$X_U3.REF_AtoD5.Q1 X$X_U3.REF_AtoD6.Q1 X$X_U3.REF_AtoD7.Q1
X$X_U3.REF_AtoD8.Q1 X$X_U3.REF_AtoD9.Q1 X$X_U3.REF_AtoD10.Q1
X$X_U3.OUT__AtoD1.Q1 X$X_U3.SS_OVR_AtoD1.Q1 X$X_U3.SS_OVR_AtoD2.Q1
X$X_U3.35_AtoD1.Q1 X$X_U3.BURST_AtoD1.Q1 X$X_U3.XU14.60_AtoD1.Q1
X$X_U3.XU14.56_AtoD1.Q1 X$X_U3.XU14.56_AtoD2.Q1 X$X_U3.XU14.56_AtoD3.Q1
X$X_U3.XU14.56_AtoD4.Q1 X$X_U3.XU14.56_AtoD5.Q1 X$X_U3.Q_AtoD1.Q1
X$X_U3.Q_AtoD2.Q1 X$X_U3.XU14.42_AtoD1.Q1 X$X_U3.LINE_OVP_AtoD1.Q1
X$X_U3.LOAD_OVP_AtoD1.Q1 X$X_U3.XU2.80_AtoD1.Q1 X$X_U3.CLK_130K_AtoD1.Q1
X$X_U3.CLK_130K_AtoD2.Q1 X$X_U3.XU2.82_AtoD1.Q1 X$X_U3.XU1.92_AtoD1.Q1
X$X_U3.XU1.95_AtoD1.Q1 X$X_U3.XU1.95_AtoD2.Q1
Last node voltages tried were:
NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE
(N01151) .0504 (N02746) 400.0000 (N02767) .0170 (N02817) .0170
(N02981) .0177 (N03170) .0029 (N03174) 918.6E-12 (N03190) 296.1E-06
(N03863) 23.53E-06 (N03926) 1.038E-06 (N05245) 1.2649 (N05339) 1.2649
(N06585) .7882 (N06669) 1.2607 (N07812) .8312 (N08836) .0034
(N10436) .5472 (N10440) .0016 (N10947) 1.1277 (N11467) .0032
(N12459) .0494 (N12931) .0188 (N12935) 290.6E-06 (N14017) .0029
(X_U2.1) 2.4950 (X_U2.2) 237.8E-06 (X_U2.3) 21.63E-06 (X_U2.4) 21.62E-06
(X_U2.5) 2.0000 (X_U2.8) 1.6784 (X_U3.7) .0498 (X_U3.9) .6586
(X_U3.Q) .1654 ($G_DGND) 0.0000 ($G_DPWR) 5.0000
(X_U3.10) 0.0000 (X_U3.11) 5.0000
(X_U3.12) 0.0000 (X_U3.15) 20.0000
(X_U3.17) 9.8575 (X_U3.18) .2255
(X_U3.24) 373.9E-06 (X_U3.31) .9472
(X_U3.32) 1.2000 (X_U3.33) 116.2E-06
(X_U3.34) 3.7866 (X_U3.35) 2.5000
(X_U3.REF) 5.0000 (X_U3.OUT_) 2.8666
(X_U3.BURST) 2.4966 (X_U3.FB_CL) 9.4665
(X_U3.OSC_CL) 9.9318 (X_U3.SS_OVR) 5.0000
(X_U3.XOP3.7) 9.9950 (X_U3.XOP3.8) 10.0000
(X_U3.XOP3.9) 9.9998 (X_U3.XPWR.2) 0.0000
(X_U3.XU1.91) 1.2500 (X_U3.XU1.92) 0.0000
(X_U3.XU1.95) 2.4943 (X_U3.XU1.97) .0900
(X_U3.XU2.78) 151.7800 (X_U3.XU2.79) 4.0000
(X_U3.XU2.80) 5.0000 (X_U3.XU2.81) .1000
(X_U3.XU2.82) 0.0000 (X_U3.XU21.4) .0895
(X_U3.XU21.5) .6569 (X_U3.XU21.6) -.0295
(X_U3.XU22.4) .7840 (X_U3.XU22.5) 2.8601
(X_U3.XU22.6) .3359 (X_U3.XU23.4) .9638
(X_U3.XU23.5) 2.8601 (X_U3.XU23.6) .5547
(X_U3.XOP3.10) .0034 (X_U3.XOP3.11) 18.1430
(X_U3.XOP3.12) 1.8570 (X_U3.XU14.40) 23.53E-06
(X_U3.XU14.41) -.1000 (X_U3.XU14.42) 353.4E-06
(X_U3.XU14.43) 14.39E-09 (X_U3.XU14.44) 23.53E-06
(X_U3.XU14.45) 27.64E-06 (X_U3.XU14.46) .4500
(X_U3.XU14.47) 3.7500 (X_U3.XU14.56) 4.9995
(X_U3.XU14.60) .2589 (X_U3.XU14.61) 3.1025
(X_U3.XU14.64) -.0058 (X_U3.XU14.65) -.0658
(X_U3.XU14.66) -.0059 (X_U3.XU14.67)-221.0E-06
(X_U3.XU14.68) -.0059 (X_U3.XU14.69) 5.0000
(X_U3.XU14.70) 0.0000 (X_U3.XU2.PWR) 5.0000
(X_U3.XU8.108) 20.0000 (X_U3.XU8.109) 20.0000
(X_U3.XU8.110) 20.0000 (X_U3.XU8.111) 2.0000
(X_U3.XU8.112) 9.8575 (X_U3.XU8.113) 1.8706
(X_U3.XU8.114) 1.8113 (X_U3.XU8.115) 9.9841
(X_U3.XU8.116) 1.3000 (X_U3.XU8.117) 9.9840
($G_CD4000_VDD) 5.0000 ($G_CD4000_VSS) 0.0000
(X_U3.CLK_130K) 5.0000 (X_U3.LINE_OVP) 0.0000
(X_U3.LOAD_OVP) 0.0000 (X_U3.XOP3.VMI) 0.0000
(X_U3.XOP3.VPI) 20.0000 (X_U3.XPWR.THR) 8.0000
(X_U3.XU1.XU8.2) .0900 (X_U3.XU14.XU8.2) 353.1E-06
(X_U3.XU14.XU9.2) 0.0000 (X_U3.XU8.XOP1.7) 9.9950
(X_U3.XU8.XOP1.8) 10.0000 (X_U3.XU8.XOP1.9) 9.9998
(X_U3.XU8.XOP2.7) 10.0010 (X_U3.XU8.XOP2.8) 10.0000
(X_U3.XU8.XOP2.9) 10.0000 (X_U3.XU8.XOP3.7) 9.9950
(X_U3.XU8.XOP3.8) 10.0000 (X_U3.XU8.XOP3.9) 9.9998
(X$X_U3.Q_AtoD1.1) .2898 (X$X_U3.Q_AtoD1.2) .1449
(X$X_U3.Q_AtoD1.3) .6803 (X$X_U3.Q_AtoD2.1) .2898
(X$X_U3.Q_AtoD2.2) .1449 (X$X_U3.Q_AtoD2.3) .6803
(X_U3.XU8.XOP1.10) 1.3000 (X_U3.XU8.XOP1.11) 18.1430
(X_U3.XU8.XOP1.12) 1.8570 (X_U3.XU8.XOP2.10) 1.8706
(X_U3.XU8.XOP2.11) 18.1430 (X_U3.XU8.XOP2.12) 1.8570
(X_U3.XU8.XOP3.10) 2.0000 (X_U3.XU8.XOP3.11) 18.1430
(X_U3.XU8.XOP3.12) 1.8570 (X$X_U3.35_AtoD1.1) .5321
(X$X_U3.35_AtoD1.2) .2660 (X$X_U3.35_AtoD1.3) 1.2037
(X_U3.XU1.XBURST.2) 5.0000 (X_U3.XU1.XU13.104) 5.0000
(X_U3.XU14.XU9.THR) .0100 (X_U3.XU8.XOP1.VMI) 0.0000
(X_U3.XU8.XOP1.VPI) 20.0000 (X_U3.XU8.XOP2.VMI) 0.0000
(X_U3.XU8.XOP2.VPI) 20.0000 (X_U3.XU8.XOP3.VMI) 0.0000
(X_U3.XU8.XOP3.VPI) 20.0000 (X$X_U3.REF_AtoD1.1) .8369
(X$X_U3.REF_AtoD1.2) .4184 (X$X_U3.REF_AtoD1.3) 1.5685
(X$X_U3.REF_AtoD2.1) .8369 (X$X_U3.REF_AtoD2.2) .4184
(X$X_U3.REF_AtoD2.3) 1.5685 (X$X_U3.REF_AtoD3.1) .8369
(X$X_U3.REF_AtoD3.2) .4184 (X$X_U3.REF_AtoD3.3) 1.5685
(X$X_U3.REF_AtoD5.1) .9606 (X$X_U3.REF_AtoD5.2) .4803
(X$X_U3.REF_AtoD5.3) 1.5499 (X$X_U3.REF_AtoD6.1) .9606
(X$X_U3.REF_AtoD6.2) .4803 (X$X_U3.REF_AtoD6.3) 1.5499
(X$X_U3.REF_AtoD7.1) .8369 (X$X_U3.REF_AtoD7.2) .4184
(X$X_U3.REF_AtoD7.3) 1.5685 (X$X_U3.REF_AtoD8.1) .8369
(X$X_U3.REF_AtoD8.2) .4184 (X$X_U3.REF_AtoD8.3) 1.5685
(X$X_U3.REF_AtoD9.1) .9606 (X$X_U3.REF_AtoD9.2) .4803
(X$X_U3.REF_AtoD9.3) 1.5499 (X$X_U3.OUT__AtoD1.1) .5877
(X$X_U3.OUT__AtoD1.2) .2938 (X$X_U3.OUT__AtoD1.3) 1.3386
(X$X_U3.REF_AtoD10.1) .9606 (X$X_U3.REF_AtoD10.2) .4803
(X$X_U3.REF_AtoD10.3) 1.5499 (X_U3.XU1.XBURST.THR) -.5000
(X$X_U3.10_AtoD1.NORM) -1.2500 (X$X_U3.11_AtoD1.NORM) 1.2500
(X$X_U3.12_AtoD1.NORM) -1.2500 (X$X_U3.BURST_AtoD1.1) .5376
(X$X_U3.BURST_AtoD1.2) .2688 (X$X_U3.BURST_AtoD1.3) 1.2949
(X$X_U3.SS_OVR_AtoD1.1) .8367 (X$X_U3.SS_OVR_AtoD1.2) .4184
(X$X_U3.SS_OVR_AtoD1.3) 1.5683 (X$X_U3.SS_OVR_AtoD2.1) .8367
(X$X_U3.SS_OVR_AtoD2.2) .4184 (X$X_U3.SS_OVR_AtoD2.3) 1.5683
(X$X_U3.XU1.92_AtoD1.1) .0825 (X$X_U3.XU1.92_AtoD1.2) .0412
(X$X_U3.XU1.92_AtoD1.3) .6917 (X$X_U3.XU1.95_AtoD1.1) .5373
(X$X_U3.XU1.95_AtoD1.2) .2686 (X$X_U3.XU1.95_AtoD1.3) 1.2946
(X$X_U3.XU1.95_AtoD2.1) .5373 (X$X_U3.XU1.95_AtoD2.2) .2686
(X$X_U3.XU1.95_AtoD2.3) 1.2946 (X$X_U3.XU2.80_AtoD1.1) .8367
(X$X_U3.XU2.80_AtoD1.2) .4184 (X$X_U3.XU2.80_AtoD1.3) 1.5683
(X$X_U3.XU2.82_AtoD1.1) .2569 (X$X_U3.XU2.82_AtoD1.2) .1285
(X$X_U3.XU2.82_AtoD1.3) .6119 (X_U3.XU1.XGREENMODE.2) 5.0000
(X$X_U3.XU14.42_AtoD1.1) .2570 (X$X_U3.XU14.42_AtoD1.2) .1285
(X$X_U3.XU14.42_AtoD1.3) .6121 (X$X_U3.XU14.56_AtoD1.1) .9607
(X$X_U3.XU14.56_AtoD1.2) .4804 (X$X_U3.XU14.56_AtoD1.3) 1.5500
(X$X_U3.XU14.56_AtoD2.1) .8368 (X$X_U3.XU14.56_AtoD2.2) .4184
(X$X_U3.XU14.56_AtoD2.3) 1.5684 (X$X_U3.XU14.56_AtoD3.1) .9607
(X$X_U3.XU14.56_AtoD3.2) .4804 (X$X_U3.XU14.56_AtoD3.3) 1.5500
(X$X_U3.XU14.56_AtoD4.1) .9607 (X$X_U3.XU14.56_AtoD4.2) .4804
(X$X_U3.XU14.56_AtoD4.3) 1.5500 (X$X_U3.XU14.56_AtoD5.1) .8368
(X$X_U3.XU14.56_AtoD5.2) .4184 (X$X_U3.XU14.56_AtoD5.3) 1.5684
(X$X_U3.XU14.60_AtoD1.1) .1247 (X$X_U3.XU14.60_AtoD1.2) .0624
(X$X_U3.XU14.60_AtoD1.3) .8258 (X$X_U3.CLK_130K_AtoD1.1) .8368
(X$X_U3.CLK_130K_AtoD1.2) .4184 (X$X_U3.CLK_130K_AtoD1.3) 1.5684
(X$X_U3.CLK_130K_AtoD2.1) .9607 (X$X_U3.CLK_130K_AtoD2.2) .4804
(X$X_U3.CLK_130K_AtoD2.3) 1.5500 (X$X_U3.LINE_OVP_AtoD1.1) .0825
(X$X_U3.LINE_OVP_AtoD1.2) .0412 (X$X_U3.LINE_OVP_AtoD1.3) .6917
(X$X_U3.LOAD_OVP_AtoD1.1) .0825 (X$X_U3.LOAD_OVP_AtoD1.2) .0412
(X$X_U3.LOAD_OVP_AtoD1.3) .6917 (X_U3.XU1.XGREENMODE.THR) -.5500
(X$X_U3.10_AtoD1.XNORM.THRESHOLD) 1.5000
(X$X_U3.11_AtoD1.XNORM.THRESHOLD) 1.5000
(X$X_U3.12_AtoD1.XNORM.THRESHOLD) 1.5000
DGTL NODE : STATE DGTL NODE : STATE DGTL NODE : STATE DGTL NODE : STATE
( X_U3.13) : X (X_U3.XU1.94) : 0 (X_U3.XU1.102) : 1
(X_U3.UVLO) : 1 (X_U3.XU1.Q) : 0 (X_U3.XU14.53) : X
( X_U3.8) : 0 (X_U3.XU1.92$AtoD) : 0 (X_U3.XU14.48) : 1
(X_U3.XU1.99) : 1 (X_U3.REF$AtoD2) : 1
(X_U3.XU14.60$AtoD) : 0 (X_U3.XU14.61$DtoA) : 1
(X_U3.QR_DONE) : 0 (X_U3.XU2.73) : 1 (X_U3.REF$AtoD7) : 1
(X_U3.10$AtoD) : 0 (X_U3.BURST$AtoD) : 1
(X_U3.XU1.XU13.105) : 1 (X_U3.XU14.56$AtoD3) : 1
(X_U3.XU2.74) : 1 (X_U3.REF$AtoD8) : 1 (X_U3.XU14.59) : 0
(X_U3.XU1.90) : 0 (X_U3.XU1.XU13.106) : 1
(X_U3.XU14.56$AtoD4) : 1 (X_U3.XU1.89) : X (X_U3.REF$AtoD) : 1
(X_U3.XU14.57) : X (X_U3.XU2.83) : 0 (X_U3.XU1.96) : 0
(X_U3.LINE_OVP$AtoD) : 0 (X_U3.XU1.95$AtoD) : 1
(X_U3.9$DtoA) : 0 (X_U3.XU14.50) : X (X_U3.XU2.84) : 0
(X_U3.XU2.80$AtoD) : 1 (X_U3.XU14.42$AtoD) : 0
(X_U3.XU14.49) : 1 ( X_U3.23) : 1
(X_U3.LOAD_OVP$AtoD) : 0 (X_U3.XU14.56$AtoD) : 1
(X_U3.Q$AtoD2) : 0 (X_U3.35$AtoD) : 1
(X_U3.SS_OVR$AtoD2) : 1 (X_U3.REF$AtoD3) : 1
(X_U3.REF$AtoD4) : 1 (X_U3.XU2.75) : X (X_U3.REF$AtoD9) : 1
(X_U3.Q$AtoD) : 0 (X_U3.XU1.XU13.107) : 0 (X_U3.XU14.62) : 1
(X_U3.XU14.56$AtoD5) : 1 (X_U3.XU2.76) : Z (X_U3.REF$AtoD10) : 1
(X_U3.XU1.100) : X (X_U3.12$AtoD) : 0
(X_U3.7$DtoA) : 1 (X_U3.XU14.54) : 0 (X_U3.SS_OVR$AtoD) : 1
(X_U3.RUN) : 0 (X_U3.XU14.51) : 0 (X_U3.XU2.85) : 1
(X_U3.XU1.97$DtoA) : 0 (X_U3.OUT_$DtoA) : 1
(X_U3.XU14.52) : 1 (X_U3.XU2.86) : 1
(X_U3.XU1.95$AtoD2) : 1 (X_U3.XU2.82$AtoD) : 0
(X_U3.XU1.87) : X (X_U3.REF$AtoD5) : 1 (X_U3.OUT_$AtoD) : 1
(X_U3.XU2.72) : X (X_U3.REF$AtoD6) : 1 (X_U3.XU1.OVR_T) : Z
(X_U3.XU14.63) : 1 (X_U3.CLK_130K$AtoD2) : 1
(X_U3.XU14.56$AtoD2) : 1 (X_U3.XU2.77) : Z (X_U3.Q$DtoA) : 0
(X_U3.11$AtoD) : 1 (X_U3.XU14.58) : 1
(X_U3.XU1.93) : 0 (X_U3.CLK_130K$AtoD) : 1 (X_U3.XU1.101) : X
(X_U3.XU1.88) : 1 (X_U3.REF_OK_) : 1 (X_U3.XU14.55) : X
**** Interrupt ****