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Reflections with CDCVF25081 IBIS model - Regarding

chitprad
Intellectual 1510 points
Other Parts Discussed in Thread: CDCVF25081

Hi All,

I have a customer working with IBIS model of CDCVF25081 clock buffer and is facing issues, kindly advice me on his inquiry.

"I am using the IBIS model of CDCVF25081 clock buffer.  This chip has a 25 ohm internal series termination resistor. I am doing Signal integrity analysis for the clock going from the buffer to an FPGA. I am trying to match the output impedance of the buffer to 50 ohm PCB trace by using an external series termination resistor of 25 ohms.

The other end of the 50 ohm PCB trace is connected to the FPGA. No matter which resistor value I select, the reflections are significant. The trace length is 9inches. Does the IBIS model include this 25 ohm internal resistor? What is the best way to minimize reflections in this case. Any suggestions would be helpful. The software I am using for signal integrity is Sisoft. "

Thanks in advance.

Best Regards,
C.Pradeep

 

 

 

 

  • 0
    TI__Mastermind 40295 points

    Pradeep,

    I am a modeling engineer in the Analog eLab Group. I will investigate the issue descibed by the customer and get back to you later today or tomorrow.

    Regards,

    John Miller

  • 0
    TI__Mastermind 40295 points

    Pradeep,

    Just a quick note to let you know we are looking at your inquiry.

    One question: The customer mentioned driving an FPGA via a 50 ohm transission line, and he is seeing reflections in simulations. Please forgive me if this is a trivial question (I am unfamiliar with FPGAs), but does the FPGA input offer a 50 ohm load to the PCB trace? I assume the customer has considered this, but I just want to be sure.

    Regards,

    John Miller
    Modeling Engineer
    Analog eLabs

  • 0 in reply to John Miller - Sensing
    TI__Intellectual 1510 points

    Hi John,

    Thank you for the reply.

    "As the customer is using Series termination technique, first reflection at FPGA pin should see 50 ohm load through out (infinite line) and ideally should not reflect back. So FPGA pin impedance will not have impact in this termination techique. Correct me if I am wrong."

    Thanks & Regards,
    C.Pradeep

  • 0 in reply to chitprad
    TI__Mastermind 40295 points

    Pradeep,

    I spoke with one of the apps engineers in the interface & clocking group.

    His suggestion is first try removing the external 25 ohm resistor. If that does not reduce or eliminate the reflections,  then try looking at the parasitics that might be present in the PCB layout path.

    If these suggestions don't help, please ask the customer if he/she is willing to share some additional details on the design they are trying to simulate.

    In the meantime I will see if the customer's application is available to us internally so we can try to reproduce their results if they are willing to share their project files.

    Best Regards,

    John Miller

     

  • 0 in reply to John Miller - Sensing
    TI__Intellectual 1510 points

    Hi John,

    Thank you very much for the help. Customer has come back informing that his issue is resolved. Please find the customer response below.

    "From the Signal integrity simulations, the output impedance of the CDCVF25081 is 50 to 55 ohms. So there is no external resistor required. It would be of great help to designers, if TI mentions  this in the datasheet.

    Maybe there is a good reason that this is not mentioned? In that case I would like to know why    ."

    Thanks & Regards,
    C.Pradeep

     

     

  • 0 in reply to chitprad
    TI__Mastermind 40295 points

    Pradeeep,

    Thank you for the update. The customer's results seem to be at odds with the data sheet, and how we expect the model to work.

    Has he customer indicated how they determined the output impedance value from their sims?

    This would be useful information to have before we pusure the issue further.

    Regards,

    John Miller

  • 0 in reply to John Miller - Sensing
    Genius 3290 points

    Hi John,

    I am the customer.

    The setup I have is like so -

    TI clk buffer --> 50 ohm Transmission line --> FPGA

    Any CMOS gate has high input impedance. So it can be considered as an open circuit.

    (In typical RF systems, you have impedance matching at both source and destination. Series resistor at source and parallel termination at the destination.)

    The way you determine source impedance is -

    If you connect a load that is equal to source internal impedance, the output voltage of the source will divide equally between the source internal impedance and the load.

    So when I connected the output of clk buffer to 50 ohm Tx line, I saw (3.3/2) volts at the output of the clock buffer.

    The sourcing and sinking impedance of the clk buffer are slightly different (sourcing is 55 ohms, sinking is 50 ohms).

    Now, coming to the FPGA. When the load is open or high impedance, all the transmitted energy is reflected back. So, if the load sees 1.65V, it will reflect all of it back resulting in 3.3v.

    Why TI does not mention the impedance is a mystery to me. Maybe there is a good reason?

     

    Regards,

    -Hithesh

     

     

     

     

     

  • 0 in reply to Hithesh
    TI__Mastermind 40295 points

    Hithesh,

    Thanks for the reply.

    I checked with an engineer in the product group. The output impedance of the device is a sum of an active resistance of about 25 ohms and a passive, internal resistance of 25 ohms.

    Please let me know if you have any questions.

    Regards,

    Joohn Miller

  • 0 in reply to John Miller - Sensing
    Genius 3290 points

    John,

    Thanks for the update.

    John Miller said:

    Hithesh,

    Thanks for the reply.

    I checked with an engineer in the product group. The output impedance of the device is a sum of an active resistance of about 25 ohms and a passive, internal resistance of 25 ohms.

    Please let me know if you have any questions.

    Regards,

    Joohn Miller

     

    That is exactly what i expected. But Why isn't this mentioned in the datasheet.

    If TI can mention it, it would save us a lot of time.

     

  • 0 in reply to John Miller - Sensing
    Genius 3290 points

    John/Pradeep, 

    I have one more question regarding the IBIS model of the buffer in question.

    In the IBIS file the model name assigned to output pins is CDCVF25081_OUT

    But that model is not present in the IBIS file at all.

    The models in the file are -

    CDCVF25081_PLL

    CDCVF25081_BUF

    CDCVF25081_IN

    CDCVF25081_CTRLIN

  • 0 in reply to Hithesh
    TI__Expert 3555 points

    Hithesh,

    In the IBIS file of this model the CDCVF25081_OUT is modeled. This output buffer is captured under the [Model Selector] section at the beginning of the file on line 88. In this statement, the buffer behavior of CDCVF25081_OUT is split into two separate conditions --> CDCVF25081_BUF and CDCVF25081_PLL. These two modes of operation are described in the Data Sheet's Funcion table (pg 1). In both cases (CDCVF25081_BUF and CDCVF25081_PLL) the Model_type is Output and you will find I-V data for power_clamp, ground_clamp, pull_up, and pull_down. You will also find data for the rising and falling edge transient responses.

    Bonnie Baker