This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TINA/Spice/SN65LVDS100: SN65LVDS100 IBIS model

Part Number: SN65LVDS100
Other Parts Discussed in Thread: TINA-TI,

Tool/software: TINA-TI or Spice Models

Hi team,

I'm planning to verify using the IBIS model of SN65LVDS100.

I downloaded the IBIS model, there are two things I want to check.

#1

Y, Zpin output signal is constant regardless of Receiver Input signal of A, Bpin.

I investigate the cause, but is there any possibility that this model is fixed output?

We will use it about 100MHz.

#2

The variation of the model is NA, but is there model specified for MIN / MAX?

Since we want to confirm that there is no problem even in the worst condition, we want to obtain a model with min / max.

Best regards,

Tomoaki Yoshida

  • Yoshida,

    Per IBIS spec, the models are for individual buffers. In other words, the model does not know pin Y repeats pin A, etc. I am not sure what your simulation tool is, but if you select an output buffer, you should be able to get a toggling waveform.

    The model is from 2002, i don't know why the min/max corners were not included. Since the device is very old, it is unlikely we will be able to get that information. Nevertheless, feel free to talk to your local TI representative about what you need. They may be able to help you find more details.

    Thanks,
    JC

  • Hello Yoshida-san,

    #1) In IBIS simulation, output pins (for this case Y and Z) should be configured as an output. Please ensure that this is the case.

    In addition, the receiver input shouldn’t affect the output characteristic. In other words, signal applied at  the input is not carried over at the output. If you can share with me your simulation set up, I can be more specific as to what can be a root cause. Please let me know.

     

    #2) It appears the model is very old and MIN/MAX corners were not modeled at the time of the development, which is not unusual for an old model.

     

    Thanks,

    - Eric Kim (Online Design Tools team)

  • Hi Eric-san,

    Thank you for your support.

    #1)

    I checked that the output pin is set as output.

    We also have toggle output.

    However, since the SN65LVDS100 is a buffer, I would like to confirm by buffering the input signal.

    In other words, we do not have this model, we need a model whose output varies depending on the input signal.

    Is there a model that outputs buffered input signals like that?

    We would like to use it as buffer of 150 MHz to 200 MHz LVDS.

    #2)

    I understand that.

    Best regards,

    Tomoaki Yoshida

  • Yoshida-san,

     

    #1) I am glad to hear you were able to see toggling output.

          Unfortunately, what you describe (“we need a model whose output varies depending on the input signal”) doesn’t exist especially in the context of IBIS model.

          Encrypted Spice netlist will be an ideal solution for you. But there are problems with this approach:

          a) Considering the age of the device, spice netlist generation is very difficult. This is typically done by the product line involved. So you might have to contact them directly.

         b) Even if the spice netlist is generated, depending on the tool you used, the netlist might not be supported. So you should check the simulation tool's capabilities first.

     

    Please let me know if you have further questions.

    Thanks,

    -Eric Kim (Online Design Tools team)

  • Hi Eric-san,

    Thank you for your support.

    I understand that I will consider how to do it after that.

    Best regards,

    Tomoaki Yoshida