TINA/Spice/TPS53667: Simulation Error and Extra Pins on Model

Hi Russell
The serial VID protocol has not been implemented in the model. However, the following registers can be programmed using a parallel
interface using eight bits for data and a clock. The command data bits are sampled on the falling edge of the clock CLK.
The CMDDATA[7:0] and CLK pins are specific to the model and are not a part of the IC. The following commands are supported:
The CLK requires a minimum on-pulse width of 100ns and a minimum off-pulse width of 100ns. The
voltages for CMDDATA and CLK pins are specified using the stimulus input. The logic threshold for
CMDDATA[7:0] and CLK pins is 0.5V. The registers are write only and cannot be read.
You can see an example of how to dynamically change the output in the PSPICE model's application schematic setup.
Thanks
Ranjani