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TIDA-00364: Capacitor Board- Capacitor Selection and Calculation of values

Pallab Sarkar34
Prodigy 210 points
Part Number: TIDA-00364

There are 30 capacitors used for the capacitor Board PCB, of 120 micro Farads ,as seen from the schematic.

How was this value obtained and what is the reason for using these many capacitors in parallel? Is it to keep a stiff DC input?

Also, could you please explain the auxiliary circuit in the schematic of CB_PCB where 200K and 10 K resistors along with 0.01 micro farad Capacitor is used. I think it is for filtering purposes. Please share your views.

Regards,

Pallab

  • 0
    TI__Expert 5130 points
    Pallab, hello and thank you for your interest in Texas Instruments and our TI Designs. I noted that you have multiple E2E questions for this specific design. To help you get expedited responses to you questions, it is perhaps best if you simply hit "reply" to the last response from the TI engineer instead of submitting a different E2E thread each time.

    Doing things this way you will avoid additional processing delays and the response goes direct to the design owner you were already dialoguing with. When it is a new E2E thread, the new thread has to be reforwarded to the same engineer, who is actually in another global region from the team that moderates this particular E2E forum.

    Hope this information is helpful. Your question has been forwarded to our engineer Pawan who answered your intial queries. You shoud receive a response from Pawan within the next 1-2 business days.

    Best Regards,

    J. Fullilove
    Texas Instruments
    TI Designs
  • 0 in reply to JohnFullilove
    TI__Expert 3705 points
    Pallab, Thanks for your interest in this TIDA. The goal of the reference design is to show the paralleling of MOSFETs and their gate drive and it is not a complete end product/inverter. As such the DC link capacitance has not been optimized. The selection of DC link capacitor depends on the voltage rating, capacitance and ripple current rating. It is up to the customer to decide/optimize the value based on multiple parameters. You may refer to IEEE papers or power electronics text books for more theory on DC link capacitor selection. We will be glad to help on query related to TI parts.

    The voltage divider comprising of 200k and 10k is as a provision to measure inverter phase voltages. This can be connected to the ADC pins on your MCU. I hope this answers your query.

    Regards,
    Pawan
  • 0 in reply to JohnFullilove
    Prodigy 210 points

    Hi John,

    Thanks for informing and helping out. I would like to know if there is a possibility to continue the discussion even if it is declared as resolved by the user.

    Regards,

    Pallab

  • 0 in reply to JohnFullilove
    Prodigy 210 points

    Hi Pawan,

    Thanks for your inputs. I did go through couple of references (papers and materials) to understand the DC Bus capacitance calculation. I was just curious to know if anything similar was done for TIDA-00364, as this information was not available in the design document.

    It would be of great help if you could please answer the following queries:

    1. I have the requirement to run a 2.5 KW machine, unlike the 5KW motor as mentioned in the document. In that case, is it okay if I populate 2 or 3 MOSFETs in parallel,because of the less current ratings; instead of all 5. I understand the advantages of increasing the no. of MOSFETs in parallel w.r.t reduction of losses, as given in the document. However, would it be really needed if the rating itself is lowered.

    2. As the number of MOSFETs in parallel increases, their distance from the common gate driver also increases. Does this affect the performance, in terms of switching the later/farther MOSFET(s), because of the increased distance, as compared to the nearer ones? If so. How?Please clarify.

    Regards,

    Pallab

  • 0 in reply to Pallab Sarkar34
    TI__Expert 3705 points
    Pallab,

    1. For deciding the number of FET's to be used in parallel the key thing is to ensure that the junction temperature of the FET's is within limits at the maximum operating temperature. First the power dissipated per FET has to be calculated. Then the maximum junction temperature rise can be estimated using the thermal model shown in the design guide (For accurate analysis a thermal simulation will be required).

    2. There are multiple parameters affecting the switching of FET which is mentioned in the design guide section 2.2.3.2. Gate drive distance is just one of them. In general try to keep distance from the common gate driver to each FET as similar as possible in the layout. For drive inverter where you switch fairly slow minor variations should not be an issue. In your case if you end up using lesser number of FETs in parallel, the distance reduces further.

    Regards,
    Pawan