TINA/Spice/LMK04832: Hyperlynx Simulation - Clock Outputs Look Bad

Tool/software: TINA-TI or Spice Models

I pulled the LMK ibis model into Hyperlynx vx2.3.  I have a sim with Oscout going to an SI5332 and another with the clock outputs going to a Xilinx MGTRREFCLK.  The clocks look terrible in both cases with 240 ohm terminations.   The N side is the worst.  If I use 50 Ohm terminations or the 50Ohm on each side with 53ohm to ground termination to the SI5332, it looks better out of the LMK, but it doesn't perform well at the receiver. Nothing looks good with the XIlinx FPGA, but it is better with 50Ohms, than 240. I have 0.01 uF decoup caps on the lines like the receiver suggests.   Another co-worker is simulating the LMK with an Altera FPGA and his looks better than mine, but still pretty terrible.  The pairs aren't even crossing each other (which makes sense considering the N side is hovering from 1.8V to 2.3V (P side looks like a normal wave from 1.5 to 2.5V)  We have the model setup for 3.3V LVPECL 2.0.  Help! Thanks.