TIDA-01022: how to choose sample rate, data rate, and clock source

Hi Michael,
TIDA-01022 has four channels(2x ADC12DJ3200) and each channel can operate 3.2 Gsps at dual channel mode , 6.4 Gsps at single channel mode.
Also 2xADC12DJ3200 can be interleaved onboard to increase sample rate 12.8 Gsps.

Let me know what sample rate you are looking ? so i can help you how to generate files .
TIDA-01022 design guide has test results and configuration files helps to find ADC performance at 2.7 Gsps.

Hi Michael,

In TIDA-01022 hardware  along with ADC, the  LMK61E2, LMK04828 and LMX2594 to be configure for ADC clock generation.

The ADC_SYSREF, FPGA_CORECLK, FPGA_REFCLK and FPGA_SYSREF to be calculated based the ADC device clock (ADC_DEVCLK) requirement and SERDES lanes used for capture. To achieve a 6.4 GSPS sample rate, the following clocks were generated by the on-board clocking solution.

ADC_DEVCLK = 3.2 GHz; to operate ADC in 6.4 GSPS single-channel mode

ADC_SYSREF =40 MHz

FPGA_CORECLK = 320 MHz

FPGA_REFCLK = 320 MHz

FPGA_SYSREF = 40 MHz

SERDES lane rate = 8

Both the LMX2594-A and LMX2594-B devices are configured to generate 3.2 GHz at RFOutA for DEVCLK and 40 MHz at RFOutB for SYSREF from the 40-MHz reference at the OSCin input which is connected to the OSCout of the LMK04828 device via the LMK00304 clock buffer.

The general ADC configuration file generation for JESD lane,  JMODE selection explained under 8.3 Initialization Set Up in ADC12DJ3200 datasheet.

1. Feed the input signal at J12 SMA connector

2. Program LMK61E2 as 40 MHz reference generation using  USB2ANY programmer via J32 header with J62 Jumper  

   removed.

3. Program the attached configuration file using HSDC TID GUI "Lowlevel page tab" in order and run the HSDC Pro  

  GUI   for capture data.

Note: 1. Attached file for JMODE0, 3.2 DCLK , 6.4 Gsps single channel mode

2. Further hardware setup refer (FIG.19) and SNR measurement Test in TIDA-01022 user guide

JMODE0.zip

Hi Michael,

More no of samples can be selected from "Analysis window (Samples)" in HSDC Pro GUI. 

Hi Michael,

VIN_N connected to INA+ adc12dj3200 (Channel 1 of both ADC1 and ADC2) for easy PCB routing to avoid via at inputs and maintain symmetry across all channels. ADC data can be inverted at software.