**Part Number:**TIDA-00753

**Other Parts Discussed in Thread:**LMV321

Hi,

an additional confusing points have been found in either, chapter 4.2 and table 3, if points 1-3 consider only error due to finite Aol of LMV321.

1. At the begining the term "gain" has been used "*Because the input full-scale voltage is very low, a gain stage is required to obtain a better SNR*.". Afterwards, in table 3, Reference No. 3, the Ideal Gain has been calculated as attenuation (0.01999). Is this "Ideal Gain" closed-loop gain or something else?

2. REFERENCE NO2: Does *Bopen* include mismatch between resistors R1 and R2? ( e.g. R2 = 49.8501k (-0,1% tolerance) and R1=1,001k (+0,1% tolerance))

3. REFERENCE NO 3: If R1=1k and R2=49,9k, why the IdealGain is 0,0199 instead 49,9? I mean, if Acl=Aol/(1+Aol*Beta), and the Figure 9 suggests Beta=R1/R2, than ideal closed loop gain should be R2/R1.

For the inverting amplifier, ideal closed loop gain will be -R2/R1, and that is 49,9 (if Aol is endless). Since Aol is not endless, the real closed loop gain for inv. amp will be:

Aclosed=-[Aol*R2/(R1+R2)]/[1+Aol*R1/(R1+R2)]=49,73 (tolerance of Resistors is not incluede). (References: https://m.eet.com/media/1152885/24987-56190.pdf, http://www.ti.com/lit/an/slyt374/slyt374.pdf)

It means that Gain error due to finite Aol (15000 for LMV321) will be 0,34%. If mismatch of 0,1% resistor will be included, it will be 0,54%.

4. REFERENCE 11: Is the input bias error calculated here as RTO value? I am asking due to noise gain (1+R1/R2) in the expression?

Br

Josko