Part Number: PMP5711
Dear TI experts,
Is there any minimum load at output side Requirement for PMP5711?.
Regards
Aneesh
This thread has been locked.
If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.
Hello Aneesh, the design is fine for zero load, best regards, Bernd
Hello Aneesh,
the error amplifier is on secondary side, see U2A, so output voltage is controlled directly at output capacitors,
using the remote sense lines directly at the point of load.
At forward topology output energy is controlled by the V x sec product, so reduction of duty cycle results in less energy at the output.
At light load or zero load the controller starts to skip pulses, but auxiliary is kept alive by internal J-FET.
You could study data sheet page 19/22 on this.
And it works, you could study my test report page 2, figure 1/2, start up and shutdown are shown at full load 35A and zero load 0A.
Best regards, Bernd
Hello Aneesh,
this won't work properly for single ended FORWARD topology by just adding a secondary winding at xfmr;
it's not like a flyback, so just think about a dual winding for output filter inductor...
Simply go for LM5034 and operate the two REGULATED 15A power stages 180 degs out of phase...
Best regards, Bernd