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PMP10116: PMP10116 not stable

Franz Schellhase
Expert 3605 points
Part Number: PMP10116
Other Parts Discussed in Thread: UCC28063A,

Hi team,

I have a customer that is testing reference design PMP10116, which uses UCC28063A. Unfortunately it isn’t working in a stable manner when the output voltage is adjusted.

Their suspicion was that UCC28063A needs a much higher current draw at startup (like stated in the datasheet) than what the voltage divider of R11, R17 and R21 can deliver. To mitigate this they decided on using a DCDC converter instead to provide power for the device like recommend in UCC28063As datasheet.

But it is still not stable even though voltage can be adjusted in a narrow range. How can this be resolved?

Thank you,

Franz

  • 0
    TI__Intellectual 2610 points
    Franz,

    Thanks for reaching out to us. I have looped the designer, Flo, in.

    How fast is the customer trying to slew the output? I wonder if the power supply is hitting current limit during voltage increase. Also, this power supply cannot sink current from the output, so ramping the output voltage down may be a function of the output capacitance and load current during this transition.

    Ryan
  • 0 in reply to Ryan Manack
    TI__Prodigy 430 points
    Hi Franz,

    the current through the voltage divider R11, R17, R21 just charges the capacitor C28. When the UVLO threshold voltage is reached the controller starts switching and will be supplied from the auxiliary winding (BIAS) of the transformer T1. The bias voltage depends on the output voltage. The PMP10116 is only regulating the output current (not the voltage). Therefore a load must be connected that the resulting output voltage is between 215V - 285V. The load can be a resistor or a LED. I recommend to measure the bias voltage during startup. It must raise up to a voltage between 16V and 22V (depending on the load).
    Another problem could be the stability, because the total open loop depends on the load. The compensation network should be optimized for the specific load. Therefore connect a frequency response analyzer (for example venable) to the resistor R26 and measure the total open loop in the lab. Then optimize the compensation network to achieve a phase margin of about 60degree and a gain margin of at least 10dB.
    Thank you.
    regards,
    Florian