Hi team,
Could you help to confirm and clarify my understanding and questions as below about ISO7637-2 pluse 1 figure 26 and 27.
If there is a negative spike in input side (figure 26), the reverse polarity component Q3 will conduct and short Gate/Source of Q1 and Q2 to make them switch off to disconnect input and output.
Why the output is clamped in -3.25V?
Why the input is clamped in -20V?
Once there is a negative spike in input, I have the concerns on GATE pin and OVP pin, please help to clarify if these pin are over negative voltage spec.
Please also help to confirm my understanding on SEN/VIN/UVLO/EN pin.
1. SEN pin, a zener D4 will be forwarded and make SEN pin to be Vf (0.3V-0.4V), or even without zener, SEN pin can sustain -25V as datasheet 6.1 note#5.
2. VIN pin, a diode D5 will block the negative spike and won't let the spike go into VIN pin.
3. OVP pin, if a negative spike happens, the rating has only -0.3V which is not enough?
4. UVLO pin, same as #2, D5 will block the spike.
5. EN pin, same as #2, D5 will block the spike.
6. GATE pin, I have no idea what's the voltage on GATE pin will be, please help to clarify.
Many thanks for your help.
Regards,
Allen