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TIDA-00363: Relation of Tracking Rate to Sampling Frequency

gary mella
Intellectual 440 points

Part Number: TIDA-00363
Other Parts Discussed in Thread: PGA411-Q1

Referring to TIDA 00363. I have the following carifications

1. How to convert the position information to digital. Will this conversion lead to truncation errors?

2. Does tracking rate depend on the sampling frequency. For eg For a 12 bit RDC at 100 RPS, rollover takes place at 409500 counts/sec. This means every LSB changes at 2.44us. Could this mean that to detect this change in ATO, sampling rate should be atleat 2.440us or 400Khz? Will 20 KHz work?

  • 0
    TI__Intellectual 1185 points

    Gary,

    We have notified the Engineer who worked on this design. You will be answered shortly.

    Thanks,

    Jasraj

  • 0 in reply to Jasraj Dalvi
    TI__Expert 3580 points

    Hello Gary,

    thank you for your interest in TIDA-00363 reference design. Please find below my answers to your questions:

    1. How to convert the position information to digital. Will this conversion lead to truncation errors?

    [Martin] Please refer to the TIDA-00363 design guide, link: http://www.ti.com/lit/ug/tiduc21a/tiduc21a.pdf. Our solution leverages the PGA411-Q1 resolver-to-digital converter with integrated exciter amplifier and power supply, which provides a 12-bit digital angle available either through SPI or parallel port. We achieve an absolute accuracy of better than 0.2 degree in our system, which corresponds to an overall error of less than +/-2 LBS. However, as we only tested a few PGA411-Q1, please refer to the PGA411-Q1 data sheet page to get the min/max values for the Digital Tracking Loop Characteristics in 12-bit mode INL2 and DNL2.

    2. Does tracking rate depend on the sampling frequency. For eg For a 12 bit RDC at 100 RPS, rollover takes place at 409500 counts/sec. This means every LSB changes at 2.44us. Could this mean that to detect this change in ATO, sampling rate should be atleat 2.440us or 400Khz? Will 20 KHz work?

    [Martin] The maximum tracking rate of the PGA411-Q1 does not depend on the sampling rate at which you read the digital angle through PGA411-Q1 SPI or parallel port.

    The PGA411-Q1 tracking loop is based on a Type-II Pi-controller architecture, with a 20Mhz nominal clock the tracking loop updates the digital angle constantly at a 10 MHz rate (100ns). The maximum tracking rate of the PGA411-Q1 is 72 000 rpm in 12-bit mode and 200 000 rpm in 10-bit mode. Therefore the 100rps (6000rpm) as mentioned in your example is well below the PGA411-Q1 maximum tracking rate in 12-bit mode.

    The SPI supports up to 8MHz clock, while the parallel port supports an update rate of 10MHz – if your processor supports that speed. If you read the PGA411-Q1 through the SPI port at e.g. 20 kHz rate, you will get an accurate angle in 12-bit mode up to angular speed of 72 000rpm.

    Regards,
    Martin Staebler

  • 0 in reply to Martin Staebler
    Intellectual 440 points

    Hi Martin

    Kindly clarify. Am I to understand that ADC is sampled at 10MSPS to update the digital angle in period of 100ns? How was 72000RPM limit arrived for 12 bit mode?

  • 0 in reply to gary mella
    TI__Expert 3580 points

    Hello Gary,

    The PGA411-Q1 does not have an ADC, the tracking loop consists of an Analog Multiply and Subtract subsystem using dual DAC (see PGA411-Q1 data sheet figure 16)  as well as the digital tracking loop (figure 17). We do provide the maximum tracking speed in the data sheet, however we do not provide a formula or details on our internal IP, how we achieve the 72 000 rpm tracking speed in 12-bit or 200 000 rpm in 10-bit mode. 

    The maximum tracking speed defines the maximum angular speed the PGA411-Q1 will track. And 72 000 rpm is far higher than the 100rps (6000rpm) from your example, so there should be no issue?

    On the other hand, the 10 MHz is how fast the PGA411-Q1 angle data is updated. This means a new angle is calculated every 100 ns, which is independent from the resolver mechanical speed. As written earlier, by using the parallel port the angle can be read out at 10 MHz assuming the host processor supports that speed, if needed.

    Regards, Martin

  • 0 in reply to Martin Staebler
    Intellectual 440 points

    Hi Martin

    Thank you. On academic interest, please clarify. In Fig.16 reflects external circuit or is the IC a mixed signal one?(DAC multiplier etc in same chip)?

  • 0 in reply to gary mella
    TI__Expert 3580 points

    Hello Gary,

    this is all included in the PGA411-Q1. The PGA411-Q1 is a highly integrated single-chip resolver-to-digital converter. You may refer to the PGA411-Q1 data sheet block diagram in section 7.2. for an overview.

    Regards, Martin

  • 0 in reply to Martin Staebler
    Intellectual 440 points

    Sorry for opening it again. You mentioned that angle is updated every 100ns. I am presuming that total group delay, adding  analog front end and your chip put together is around 100ns? Is that right.?

  • 0 in reply to gary mella
    TI__Expert 3580 points

    Gary,

    the 100ns is the update rate of the digital tracking loop in the PGA411-Q1. Any 100ns a new digital value is available. This value will have an overall propagation delay, which depends on the passive analog input filter and the PGA411-Q1 PLL tracking loop bandwidth. PGA411-Q1 PLL tracking loop bandwidth has two modes, AMODE=0 (normal mode) and AMODE=1 (acceleration mode).

    Please refer to the PGA411-Q1 data sheet chapter 6.15 to see the step responses for AMODE=0 and AMODE=1. 

    Regards, Martin

  • 0 in reply to Martin Staebler
    Intellectual 440 points

    Hi Martin

    please clarify if the total round trip delay (inclusive of AFE and loop tracking processing delay) is within 100ns? My particular doubt is that, update rate has to be faster than shaft angular rate. If passive filter has larger delay ( say 100us, to minimize the noise) then how would it effect the tracking rate.

  • 0 in reply to gary mella
    TI__Expert 3580 points

    Gary,

    did you refer to the PGA411-Q1 data sheet chapter 6.15 to see the step responses for AMODE=0 and AMODE=1?  These figures show the angle step responses, which give an indication on the propagation delay, which is significant larger than the 100ns PLL update rate. The 100ns is just the rate at which the latest digital angle is updated. 

    For example in figure 7, a 10 degree angle step takes ~1 ms (5% to 95%) and ~2.5ms to settle to the final value in 12-bit mode with  AMODE=0. While in 10-bit mode it takes around 0.5ms (5% to 95%)  and ~1ms to finally settle with AMODE =0. We don't provide the magnitude and phase response of the PGA411-Q1 PLL racking loop. As a very rough estimate the group delay is around 0.5 settling time.

    Regards, Martin