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TMS320C6657

Misba Raja
Prodigy 30 points

Other Parts Discussed in Thread: TMS320C6657

Dear

Below mentioned controller’s timing parameters are required for DSP --- DDR3 intewrface analysis using Hyperlynx (analysis tool) and these parameters are assumed to be defined in the controller data sheet.

1. tACCSkew --------- 

1. tACCSkew ---------- Output delay skew from CK falling to Addr/Cmd/Ctl (+/–)

2. tCKDQS ------------- Output delay skew from CK rising to DQS rising (+/–)

3. DQSDQQ ------------ Output delay skew from DQS to DQ (+/–)

4. tDS -------------------- Minimum DQ to DQS setup time, with 1/4 cycle DQS shift

5. tDH -------------------- Minimum DQS to DQ hold time, with 1/4 cycle DQS shift

Kindly advice about these parameters and about the the reference document. 

  • 0
    TI__Guru**** 161600 points

    Hi,

    This information can be found in Processor Datasheet, section 5.7.7 DDR3 Memory Controller Electrical Data/Timing, the DDR chip datasheet and DDR3 Jedec Specification JESD79-3C.

    Best Regards,
    Yordan

  • 0 in reply to Yordan Kovachev
    Prodigy 30 points

    Dear

    Section 5.7.7 describes as below:

    DDR3 Memory Controller Electrical Data/Timing
    The KeyStone DSP DDR3 Implementation Guidelines specifies a complete DDR3 interface solution as
    well as a list of compatible DDR3 devices. The DDR3 electrical requirements are fully specified in the
    DDR3 Jedec Specification JESD79-3C. TI has performed the simulation and system characterization to
    ensure all DDR3 interface timings in this solution are met; therefore, no electrical data/timing information is
    supplied here for this interface.

    My concern is, if no electrical data/ / timing information is supplied for the interface, how the timing model for controller (TMS320C6657) may be generated in Hyperlynx for simulation purpose.

    Thanks

  • 0 in reply to Misba Raja
    TI__Guru**** 161600 points

    Hi,

    I think you could use the IBIS models for TMS320C6657:
       http://www.ti.com/product/TMS320C6657/toolssoftware

    Best Regards,
    Yordan

  • 0 in reply to Yordan Kovachev
    Prodigy 30 points

    Dear

    I am not aware, how to extract timing parameters from the IBIS models.

    For other processors like MPC8377 etc timing pareameters are mentioned in the datasheet. So in my opinion these should be in datasheet.

    If u can help to extract timing parameters from the IBIS model for simulation with Hyperlynx (DDR analysis). it will be great.

    Thanks

  • 0 in reply to Misba Raja
    TI__Guru**** 161600 points

    Hi,

    I am not experienced with IBIS models. However, I found a version of the DDR3 Jedec Specification JESD79-3C specification:
      http://mermaja.act.uji.es/docencia/is37/data/DDR3.pdf

    Check Section 12 Electrical Characteristics & AC Timing for DDR3-800 to DDR3-1600 and Section 13 Electrical Characteristics and AC Timing.

    As stated in the Datasheet the TMS320C6657 DDR3 controller should be fully compliant with the DDR3 Jedec Specification JESD79-3C.

    Best Regards,
    Yordan

  • 0 in reply to Yordan Kovachev
    TI__Mastermind 46460 points

    Misba, Yordan,

    We do not provide these timing parameters for our DDR interfaces. Also, the IBIS models for the DDR interface are not calibrated for timing analysis. They are solely provided for signal integrity analysis. The rationale for this support model is explained in the document Understanding TI’s PCB Routing Rule-Based DDR Timing Specification Application Report (SPRAAV0A) available at the link below. Detailed instructions specifically applicable for the C6657 are available in the DDR3 Design Requirements for KeyStone Devices Application Report (SPRABI1C) also with a link below.
    Tom