Other Parts Discussed in Thread: ISO224EVM, , TMS320F28377D
Tool/software: WEBENCH® Design Tools
hello,
I have one question regarding to ADC acquisition window. In order to achieve rated resolution, the signal source needs to charge the sampling capacitor in the ADC core to within 0.5LSBs of the signal voltage. According to TI recommendation CS should be atleast 20 X CH .The Cs is mostly just there to prevent the driving op-amp from slewing when the sample occurs. later i have seen ISO224EVM Evaluation Module SLAU733 page 3 in which after TLV6001 ,R is selected as 47 ohm and C is selected 100pf. is it right? 100pf is less than 20 times CH, S+H is 85ns and ACQPS is 16 for this . i think S+h time is too fast to charge sampling capacitor. and if ADC clock is 50MHZ then ADC conversion time is about 205ns then total sample time is 290ns, then maximum throughput will be 3.4MHZ. could you please explian why TI used C as 100pf because it not right according to TI recommendation and one more question i am using double loop controller outer loop and voltage and inner loop is current loop. usually inner loop is faster and have have high bandwidth than voltage loop. if i want current loop faster hand having faster sampling i need to reduce value of CS i mean less than 100pf so that i will be faster than voltage loop but again its S+H will be too low. and i am not sure S+H time is enough of charging of sampling and hold capacitor. if i use primary PWM 50KHZ and secondary PWM is 100KHZ to trigger ADC then sample rate will be 100KHZ. for 100KHZ ADC sample rate how much S+H i should need. for current and voltage loops. neither too fast nor too slow thanks
