WEBENCH® Tools: Reduction of Thermal resistance by adding extra copper on PCB

Hi Pritesh,

Thanks for the inquiry. Below you will find a link to a blog on how TI measures and specifies thermal impedance for our FETs. Increasing the copper pad on the PCB will definitely help to reduce the thermal impedance. TI tests thermal impedance on the minimum pad and on a 1 sq. in. pad with 2 oz. copper. The measured results for the CSD18510Q5B with the minimum pad: 109degC/W typical/136degC/w max. On the 1 sq. in pad: 40degC/W typical/50degC/W max. Another data point: for this package and die size, our thermal simulations show that the RthetaJC_top (to the top of the plastic case) is about 8degC/W. I'm not sure you should actually parallel the thermal impedance of the larger copper shape with RthetaJA. In this model, I think the copper is in series with RthethaJC_bottom and then in parallel with the path RthetaJC_top to ambient as shown in the blog. The primary path to remove heat from this package is thru the thermal pad (drain of the FET) into the PCB. This package uses a copper clip to make the connection from the source of the silicon die to the lead frame. This also provides a pretty good thermal path to the PCB. Maximizing copper for both of these connections will help with dissipating the heat generated by the FET. You can also consider using thermal vias to internal planes to help spread the heat. Sometimes this may not be desirable if the drain or source has a large switching signal that can inject noise into your board.

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By Brett Barr1 over 9 years ago in Technical articles > Power management

Hi Pritesh,

No, I don't think you can parallel the thermal impedance of the copper shape with RthetaJA. The copper is part of RthetaJA as explained in the blog I sent to you in my earlier response. The 10 x 10mm copper shape is not much larger than the actual package and minimum pad dimensions used for TI's thermal impedance testing and is far smaller than the 1 sq. in. pad also specified in the datasheet. I don't believe you will get as much benefit as you are calculating by paralleling the copper with RthetaJA. You can probably simulate this with Flotherm or ICEpak.

Can you tell me more about your application? Are you using the FET in a switch-mode application, such as motor drive or power supply OR is it used as an on/off switch such as hot swap, OR'ing or for battery protection? What are your current/power requirements for the FET? Typically, a 5x6mm SON package can dissipate about 3W maximum. You can find some "rule of thumb" power dissipation estimates by package in the technical link below.

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By John Wallace1 over 6 years ago in Technical articles > Power management

Hi Pritesh,

I did check on the pad size on the board used to make thermal impedance measurements for the MOSFET datasheet. The minimum pad size matches the recommended PCB footprint in the MOSFET datasheet with traces extending to the edges of the board to make electrical connections to the drain, source and gate terminals of the device. For the CSD18510Q5B, the thermal pad which connects to the drain, is approximately 4.5mm x 4.5mm and the overall dimension including drain, source and gate is approximately 6.3mm. Your 10mm x 10mm pad should improve RthetaJA incrementally by improving RthetaBA (board to ambient). The larger pad will have minimal effect on RthetaJC (junction-to-case). I'm just not sure how much it will improve the effective RthetaJA. You would need to simulate or test to make this determination.