Because of the Thanksgiving holiday in the U.S., TI E2E™ design support forum responses may be delayed from November 25 through December 2. Thank you for your patience.

  • State TI Thinks Resolved
  • Locked Locked
  • Replies 1 reply
  • Answers 1 answer
  • Subscribers 40 subscribers
  • Views 357 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

WEBENCH® Tools/TLV62065-Q1: TLV62065-Q1 PSpice transient Model Simulation output anomaly

huan jia
Prodigy 10 points
Part Number: TLV62065-Q1

Tool/software: WEBENCH® Design Tools

Hello:

Use the official website pspice model-SLIM249B.ZIP (110 KB) - PSpice Model

 Simulation conditions:

Simulation 1:Change R10 and R11,All other parameters remain the same,Starting the simulation, the VOUT is not 1.1V,

Question 1:Why VOUT is 1.8V?

Simulation 2:Change Iload,All other parameters remain the same,Starting the simulation, the VOUT  waveform is abnormal.

Question 1:Why VOUT  waveform is abnormal?

Thanks

  • 0
    TI__Expert 8365 points

    Hi Huan,

    For simulation 1. The project contains two test benchs.

    1.Startup 

    2. Steady.

    You have made the changes in steady test bench but ran the simulation profile for startup test bench and hence the startup test bench results are being shown.

    Please make the steady test bench as root using 'Make Root' option and activate the steady test simulation profile as shown below.

    The results are shown below.  

    For simulation 2, Please configure the Pulse source and simulation profile as shown below.

    Thanks & Regards,

    Praveen