Hi there,
- I have read that host and Controller layers could exist in separate chipsets, or they could exist in the same chipset. In the case where the host and controller are in separate chipsets, the HCI layer will be implemented over a physical communication interface (SDIO / UART / USB). In our devices, everything exist on one chip? So the host and controller are on the same chip? Why would I or a customer want to separate it for different chips?
- Where is the SW of the host / controller is implemented? For example layers like L2CAP, ATT and so on, where are they implemented and stored? Do you have any document that I could read about these implemented layers by TI?
Many thanks.