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CC2640R2F: Trigger OS-managed Interrupt from zero latency Interrupt

Moritz Hinkel
Prodigy 20 points
Part Number: CC2640R2F

Hi TI experts or members,

I have an application, where I use the Transmit FIFO interrupt of the SSI Module (asserted, whenever there are 4 or less entries in the TX Fifo) as zero latency interrupt (because timing is critical).

Within every interrupt a portion of data is written to the SSI data register and after transmission of the last packet, the interrupt is disabled (IMSC.TXIM set to 0).

What I want to do is post a Semaphore at the end of transmission. However, this is not possible within the zero latency context.

My idea was to set another Interrupt pending, which is to be handled from the Hwi context (no zero latency, therefore access to Semaphore_post()).

My questions are:

Is it even possible to pend an interrupt from Software (eg by setting the respective NVIC register)?

Is this possible from within a zero latency interrupt?

if not:

is there another solution to use Semaphore_post() directly following a zero latency interrupt (most elegant way to do this?)

Thanks a lot and best regards

Moritz Hinkel

  • 0
    TI__Guru** 101460 points

    Hi Moritz,

    Direct access to the NVIC register when using TI-RTOS is not recommended. 

    "Zero-latency interrupts do not go through the TI-RTOS Hwi dispatcher and therefore are more responsive than standard interrupts, however this feature prohibits its interrupt service routine from invoking any TI-RTOS kernel APIs directly." (see here). In other words, the zero-latency interrupts cut the line which prevents them to leverage TI-RTOS functionalities.

    The solutions I am thinking of are:

    • do not use a zero-latency interrupt, rather use a HWI.
    • use both a zero-latency interrupt and a HWI. Execute the extremely time-critical code in the zero-latency interrupt, then use TI-RTOS APIs (i.e. Semaphore_post) in the HWI.

    Best regards,

  • 0 in reply to Clément
    Prodigy 20 points

    Hi Clément,

    thanks for the fast response!

    Because of the timing constraints of my application, it is impossible to use Hwi Interrupts.

    How can I use both? As for my understanding, I have to disable the interrupt assertion within my zero latency interrupt handler (or it will be asserted and handled over and over again).

    HWREG(spiConfig.base + SSI_O_IMSC) &= ~(SSI_IMSC_TXIM);

    So, how do I get my Hwi Interrupt handler to be executed after this? Am I missing something?

    Best regards,

    Moritz

  • 0 in reply to Moritz Hinkel
    TI__Guru** 101460 points

    Hi Moritz,

    I will need to consult with TI-RTOS experts to answer your last questions.

    Please give us a week - some experts are currently out of the office due to summer holidays.

    Thank you for your comprehension.

    Kind regards,

  • 0 in reply to Clément
    Prodigy 20 points

    Hi Clément,

    I have returned from summer holidays myself.

    Is there a suggestion for my problem available by now?

    Best regards,

    Moritz

  • 0 in reply to Moritz Hinkel
    TI__Guru** 101460 points

    Hi,

    Welcome back!

    I will ask you to open a new thread. That way, the proper experts will directly be assigned to it.

    Thank you for your comprehension.

    Best regards,