I have a fielded product using MSP430F2419TPMR processor IC and CC2640F128RHBR BLE IC. The processor communicates with the BLE IC over SPI. Several units have been returned from the field at around 1 year with apparent high-current issues. Our investigation shows that the BLE IC is, possibly hanging and then resetting due to a failed internal flash page erase. From the CC2640 datasheet, "supported flash erase cycles before failure" parameter is rated at 100,000 cycles. The MCU in this product writes data to the BLE IC over SPI once every report cycle (typically 5 minutes). The BLE IC then writes this data to local flash. So we write to BLE IC flash 288 times per day or 105,120 times per year. I am still working with our SW team to understand which flash pages are being erased and re-written every cycle (all of flash, just some sections, are these sections randomized to load balance P/E cycles, etc.). I have the following questions regarding CC2460 flash endurance and debug/investigation efforts:
- Does TI employ any methods to load balance CC2640 internal flash P/E cycles across entire flash thus preventing one section of flash from having much more P/E cycles than the rest of flash?
- If TI employs some sort of P/E cycle load balancing, is it still affective if there are very few free flash blocks (flash is at or close to capacity)?
- The minimum number of flash cycles guaranteed by TI for this part is 100,000. Is there margin beyond that number, or can we expect some CC2640 ICs to experience flash erase failures once 100,000 P/E cycles is exceeded?
- Would a flash erase failure cause the CC2640 to hang?
- Is there any way (perhaps using TI Smart RF Flash Programmer 2) to determine how many P/E cycles have been executed against a given block/page/sector of flash? …or maybe a way to program/erase individual blocks/pages/sectors of flash to definitively prove that we have a flash erase issue?
Thanks for any help you can give.
Regards,
Dan C
