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CC2541: Timer3 overflow irq takes longer time then expected

Part Number: CC2541

I am trying to make sense of the cc2541 clock and timer3,but for some reason I get a longer time period then expected.

My board is running with 32Mhz external oscillator and I configures the clock as follow:

CLKCONCMD = (CLKCONCMD & ~(CLKCON_OSC | CLKCON_CLKSPD)) | CLKCON_CLKSPD_32M;

And Timer3:

T3CTL = T3CTL_DIV_1 | T3CTL_MODE_FREERUN | T3CTL_OVFIM | T3CTL_CLR | T3CTL_START;

in the Time3 isr function, I toggle an output and monitor it with a scope. The scope shows a square signal at about 32khz, or a period of 32uS.

If I correctly understand the configuration, Timer3 should be incremented 32M/sec and the isr should be invoked 32M/256 /sec. resulting a period of about 8uS, which is about 4 times shorter from what I actually get.

What am I missing ?

Here is my isr

#pragma vector = T3_VECTOR
__interrupt void t3_isr(void)
{
    static uint8 on=0;
    // Clears the module interrupt flag.
        T3OVFIF = 0;
        P1_0 = on; // toggle the output
       on=!on;
   // Clears the CPU interrupt flag.
      T3IF = 0;
}

  • Hi Itamar,

    On reset, CLKCONCMD.TICKSPD is a value of 1 so the time tick speed is 16 MHz.  A 32 kHz square wave means that the interrupt is oscillating the P1_0 pin every 15625 ns (1/64 kHz) which is nearly equivalent to 256 divided by 16 MHz.  I hope this is able to explain why you are observing the interrupt rate described.

    Regards,
    Ryan

  • Hi Ryan

    You are right about the On Reset value but I set CLKCONCMD  to zero:

    CLKCONCMD=0;

    and T3CTL  to 0x18

    T3CTL=0x18;

    So both the clock and timer3 should be running at 32Mhz

    Since the 8 bit Timer3  overflows every 256 counts, I should get frequency of 32Mhz / 256 =125 Khz

    but all I get is 31250 Hz which is 4 times lower

    What should I do to get a better (higher) frequency ?

  • Can you use the debugger to confirm that those are the final register values after initialization and while operating?  Have you considered using another control mode which evaluates T3CC0 instead of relying on the 0xFF overflow?

    Regards,
    Ryan

  • Yes I can verify that these are the values.

    I thinkI found what I was missing:

    I am incrementing two 32 bit numbers inside the isr and this adds about 8 uS to each output transition period,

    I can get the expected transition period if I don't increment anything just toggle the output.

    The transition period should be : 1 /(32000000/256) = 0.000008. about 8 uS

    Incrementing only one of the numbers just before exiting the ISR add 2 uS for a total of 10uS (instead of 8uS as expected)

    Thanks for your help