This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

CC2642R-Q1: More than 83 flash writes to a single wordline

Part Number: CC2642R-Q1


The technical reference manual states that the flash should be erased if more than 83 writes are to be performed on a single wordline.

We have created the following code using TI Driver to check the behavior in this case.

    for(uint16_t count=0;count<256;count++)
        uint8_t tw_buff = 0xFF;
        for(uint8_t subcount=0; subcount<8;subcount++)
            tw_buff = tw_buff & (~(0x01 << subcount));
            ret_list2[count*8+subcount] = NVS_write(nvsHandle2, count, &tw_buff, 1, NVS_WRITE_POST_VERIFY);


This code sets all the bits in the wordline to 0 one by one.

The technical reference manual describes it as follows:

"If more than 83 write operations are performed before re-erasure, one may see unwritten bits in the row that are erased (in a logic 1 state) become programmed (change to a logic 0 state)."

Therefore, we expected NVS_STATUS_ERROR to be returned from some point by executing NVS_write() with NVS_WRITE_POST_VERIFY for every bit.

However, the result was that writing to all bits returned NVS_STATUS_SUCCESS and the flush value was written as intended.

Is there any misinterpretation?

  • Hello Yoshiaki,

    You can review NVSCC26XX_write from source\ti\drivers\nvs\NVSCC26XX.c to further understand the operation of NVS_write.  MAX_WRITES_PER_FLASH_ROW is only evaluated if NVSCC26XX_INSTRUMENTED is defined, and even then it will cause the device to spin in a while forever loop instead of returning an error.  You can copy the NVSCC26XX.c file directly into your project's workspace and modify it accordingly if you would like to further debug or change its behavior.


  • Thank you for your prompt reply.
    I have checked the code and it appears that this will only hold scoreboard when power is on.

    I have two questions.
    1: I take it that MAX_WRITES_PER_FLASH_ROW is a limit between erase to erase and therefore the state of the power supply is irrelevant, is this incorrect?
    2: Is it correct to interpret MAX_WRITES_PER_FLASH_ROW as the approximate number of times it is guaranteed to work, and that the hardware behavior is not defined when this is exceeded?
    In other words, it may or may not work correctly beyond 83 times?

  • The power supply should be irrelevant, however power cycles will reset the existing scoreboard count.  Proper flash behavior past the MAX_WRITES_PER_FLASH_ROW is not guaranteed.  NVOCMP operation, <sdk directory>\source\ti\common\nv\nvocmp.c, is recommended for advanced NV use since it optimizes flash access by cycling through compaction/active pages while creating new items and marking old ones as inactive.