• State Resolved
  • Locked Locked
  • Replies 6 replies
  • Subscribers 52 subscribers
  • Views 366 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

CC2340R5: Coremark iterations per second

bob frankel
Expert 2470 points
Part Number: CC2340R5


the datasheet only quotes power consumption when running Coremark....

since someone has presumably run the benchmark, how many Coremark iterations per second (divided by the 48 MHz frequency) can be achieved???  the number of normalized iterations should be in the ~1-3 range....

ideally, there is some project for some compiler with some set of optimization flags that could be viewed as a reference....

  • 0
    TI__Expert 5575 points

    Hi Bob,

    I did not find something in the material that is available for me. I forwarded it internally and we are reaching out to you as soon as we found a solution.

    This might take some time.

    Regards,

    Alex

  • 0 in reply to Alex Paul
    Expert 2470 points

    thanks....  i have the Coremark sources, but the real information lies with which compiler you used and with what optimization settings....

    FWIW -- there is a "power-centric" benchmark from EEMBC (ULPMark) which includes a "Coremark iterations per mJoule" score....  an interesting measure of how efficiently the MCU consumes power when active....

  • 0 in reply to bob frankel
    TI__Guru**** 220277 points

    Hi bob,

    I apologize for the delay as it was my responsibility to get back with you on this E2E thread.  I asked the TI Validation Team and here is their response: "The CoreMark images were created using IAR 9.32.2, with Compiler optimizations as High (Speed) with no size constraints"

    I hope this helps,
    Ryan

  • 0 in reply to Ryan Brown1
    Expert 2470 points

    hi ryan,

    very helpful!!!!

    no rush, but could you share the actual coremark score (iterations per second) obtained by the validation team....  and given that we're optimizing for speed (with no size constraints), i'm also curious how big the actual benchmark program was (code+data)....

    thanks, bob.

  • 0 in reply to bob frankel
    TI__Guru**** 220277 points

    Hello again Bob,

    The CM/MHz reported was 2.195 CM/MHz. The code side was ~18kB since they the validation team was optimizing for speed.

    Regards,
    Ryan

  • 0 in reply to Ryan Brown1
    Expert 2470 points

    i did manage to create a CCS project that included the standard CoreMark source files....  using the TI armclang compiler (optimizing for speed, of course), my image size was 17314+1509+286+2372 (text+const+data+bss).... having compared IAR with CLANG in other settings, size/speed performance is roughly comparable....

    i also measured CM iterations per second at 100.67, which then divided by CPU clock frequency (48) yields a CM score of 2.10 -- which is actually quite competitive for an M0+ CPU....  (i think this aligns with your 2.195 score....)

    through some "language optimization technology" i've been refining, my version of CM yields a higher 2.21 score while reducing memory footprint to just 9912+364+276+1452....

    send me a private message if you'd like to learn more....