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CC2340R5: about crystal tuning

Part Number: CC2340R5


Hi team,

My customer is tuning 32KHz and 48MHz crystal. They use active probe.  At the beginning, they find out the output waveform is not good (almost triangular not sine wave). After tuning cap load, there is no output. Please provide some guideline or document. I only find out below, but it bases on CC26xx device. Is this ok and enough for CC2340R5 ?

https://www.ti.com/lit/an/swra640g/swra640g.pdf chap 6.

My customer ask why the CC2340R5 reference design use the different cap load with the datasheet (as below) ?

  • Hi Jerry,

    I recommend not probing the crystals while the device is active. In fact probing the 48 MHz crystal while the device is active can cause damage.

    The guidelines in SWRA640 are valid although the software is different and the value for capacitance with the onboard capacitors will be different. For the 48 MHz clock the customer can track the output frequency from the radio since any deviation of the crystal frequency will result in the same deviation in carrier frequency. For the 32 kHz clock the crystal can be monitored via DTB0 (digital test bus on DIO19). I don't believe there is a driver library function for this at this time but the following register writes should output the clock:

    /* Pick clock in CKDM for observation. Select input 0xF in mux
    Select clock to output on DTB[0]
    0h = Select CLKULL (24 MHz during ACTIVE, 32kHz during
    STANDBY)
    1h = Select CLKSVT (48 MHz)
    2h = Select CLKADC (48 MHz)
    4h = Select tracking loop reference clock
    7h = Select LFCLK (selected by LFCLKSEL.MAIN)
    Ah = Select HFOSC after qualification
    Ch = Select HFXT divided by 8
    Dh = Select HFXT
    Eh = Select LFOSC
    Fh= Select LFXT
    */
    HWREG(CKMD_BASE + CKMD_O_DTBCTL) |= (0xF << CKMD_DTBCTL_CLKSEL_S);
    // Enable observability from CKMD
    HWREG(CKMD_BASE + CKMD_O_DTBCTL) |= CKMD_DTBCTL_EN;
    // Select DTB from CKMD in ULL signal MUX. Select input 0x1 in mux
    HWREG(IOC_BASE + IOC_O_DTBCFG) |= (0x1 << IOC_DTBCFG_ULLSEL_S);
    // Select [2:0] from DTB bus to be output to the pads. Clear PADSEL bits to '000'
    HWREG(IOC_BASE + IOC_O_DTBCFG) &= ~IOC_DTBCFG_PADSEL_M;
    // Enable DBT bus to output observed signals. Set bit 0 to '1'
    HWREG(IOC_BASE + IOC_O_DTBOE) |= IOC_DTBOE_EN0;
    // Set PORTCFG for DTB0 (DIO19) to DTB function
    HWREG(IOC_BASE + IOC_O_IOC19) |= IOC_IOC19_PORTCFG_DTB;

    As for the data sheet values and the schematic, the 32 kHz crystal has a load capacitance of 7 pF which meets the data sheet requirement. The 48 MHz crystal has a load capacitance of 7 pF which also meets the data sheet requirement.

    Best Regards,

    Jake