CC2340R5: LFCI usage, using DIO4 to expose clock

Lenio Cacula

Part Number: CC2340R5
Other Parts Discussed in Thread: SYSCONFIG

I want to use an external 32kHz signal via LFCI (DIO3) and also want to make the same signal external via DIO4 pin.

I have a Launchpad from which I removed the low frequency crystal. The device continued to advertise and was able to connect as usual, even though I configured DIO3 to work as LFCI:

I have a warning as you can see in the picture indicating "not pinned out". I am not sure of the implications of it.

I also want to configure DIO4 to make the same clock externally available. I don't see that as an option in SysConfig. Can you please tell me exactly how to execute all of this?

over 2 years ago

0 Ryan Brown1 over 2 years ago

TI__Guru**** 223757 points

Hi Lenio,

I recommend that you check the LFCLKSEL register from the CCS or IAR debugger to confirm that EXTLF has been selected and is being used for your application. I am not observing the same SysConfig behavior in the SimpleLink F3 SDK v7.40 basic_ble example when I attempt to replicate your steps:

You can refer to the Debugging LF/HF Clock Output section of the BLE5-Stack Debugging Guide for instructions to map LF crystal clock signals to an available pin.

Regards,
Ryan

0 Lenio Cacula over 2 years ago in reply to Ryan Brown1

TI__Genius 17160 points

At the moment I'm focused on making the LFXT signal available through DIO24 (this is a different pin from my original post). I was able to make it work with DIO19 as in the example, but now I'm working to switch it over to DIO24. For that I have to enable DTB5, instead of DTB0 like in the example, correct? I am struggling however on how to properly setup the multiplexers - can you please offer some help? Here is my code so far:

    uint8_t clockSrc = 0xF; //for LF crystal clock

    // drive output low first
    GPIO_setConfig(24, GPIO_CFG_OUTPUT | GPIO_CFG_OUT_LOW);

    // Configure the IOC.IOC19.PORTCFG MMR to select DTB
    HWREG(IOC_BASE + IOC_O_IOC24) &= ~IOC_IOC24_PORTCFG_M;
    HWREG(IOC_BASE + IOC_O_IOC24) |= IOC_IOC24_PORTCFG_DTB;

    // Make sure the DTB mux selects in IOC (and if required in
    // source clock IP) are reset that zero is driven on DTB0.
    // ULLSEL mux select (select CKMD)
    HWREG(IOC_BASE + IOC_O_DTBCFG) &= ~IOC_DTBCFG_ULLSEL_M;
    HWREG(IOC_BASE + IOC_O_DTBCFG) |= 0x1 << IOC_DTBCFG_ULLSEL_S; // 0x1 to route CKMD to DTB0


    // Enable IOC.DTBOE.EN5
    HWREG(IOC_BASE + IOC_O_DTBOE) &= ~IOC_DTBOE_EN5_M;
    HWREG(IOC_BASE + IOC_O_DTBOE) |= IOC_DTBOE_EN5_EN;

    // select which clock (CKMD) to output on DTB5 (DTB[5])
    HWREG(CKMD_BASE + CKMD_O_DTBCTL) &= ~CKMD_DTBCTL_CLKSEL_M;
    HWREG(CKMD_BASE + CKMD_O_DTBCTL) |= (clockSrc) << CKMD_DTBCTL_CLKSEL_S;

    // enable DTB output
    HWREG(CKMD_BASE + CKMD_O_DTBCTL) &= ~CKMD_DTBCTL_EN_M;
    HWREG(CKMD_BASE + CKMD_O_DTBCTL) |= CKMD_DTBCTL_EN;

+1 Ryan Brown1 over 2 years ago in reply to Lenio Cacula

TI__Guru**** 223757 points

I do not see anything wrong with this implementation above. When I used your code in an example project, I was able to observe output on DIO24. Tomorrow I can confirm whether it is s 32 kHz square wave that represents the LFXT. Can you please clarify which SimpleLink F3 SDK version and example you are using?

Regards,
Ryan

0 Lenio Cacula over 2 years ago in reply to Ryan Brown1

TI__Genius 17160 points

I also see output the way I have it, but it's not the 32kHz signal. I see a 4ms pulse every 100ms - I'm assuming that's the advertising period, thus my conclusion that the multiplexing isn't right. I feel the explanation in the user manual about DTBCFG and ULLSEL is not complete.

I'm using the basic BLE example, running on the latest SDK 7_40_00_64.

Thanks!

+1 Ryan Brown1 over 2 years ago in reply to Lenio Cacula

TI__Guru**** 223757 points

Hi Lenio,

I apologize as yesterday's observations from my side were misleading. After reviewing the "Debugging LF/HF Clock Output" section further and cross-referencing with Chapter 18.3 of the TRM, DTB0 is the only Digital Test Bus capable of outputting the clock output. Thus the only other option than DIO19 would be DIO12, where PADSEL can re-route DTB0 to DTB13 which resides on DIO12. The initial DIO19 code and this modified DIO12 code have now been verified on my end:

    //uint8_t clockSrc = 0xC; //for HF crystal clock divided by 8
      uint8_t clockSrc = 0xF; //for LF crystal clock

    // drive output low first
    GPIO_setConfig(12, GPIO_CFG_OUTPUT | GPIO_CFG_OUT_LOW);

    // Configure the IOC.IOC12.PORTCFG MMR to select DTB
    HWREG(IOC_BASE + IOC_O_IOC12) &= ~IOC_IOC12_PORTCFG_M;
    HWREG(IOC_BASE + IOC_O_IOC12) |= IOC_IOC12_PORTCFG_DTB;

    // Make sure the DTB mux selects in IOC (and if required in
    // source clock IP) are reset that zero is driven on DTB0.
    // ULLSEL mux select (select CKMD)
    HWREG(IOC_BASE + IOC_O_DTBCFG) &= ~IOC_DTBCFG_ULLSEL_M;
    HWREG(IOC_BASE + IOC_O_DTBCFG) |= 0x1 << IOC_DTBCFG_ULLSEL_S; // 0x1 to route CKMD to DTB0

    // Map DTB[2:0] to DTB[15:13]
    HWREG(IOC_BASE + IOC_O_DTBCFG) &= ~IOC_DTBCFG_PADSEL_M;
    HWREG(IOC_BASE + IOC_O_DTBCFG) |= IOC_DTBCFG_PADSEL_DTB2TO0;

    // Enable IOC.DTBOE.EN0
    HWREG(IOC_BASE + IOC_O_DTBOE) &= ~IOC_DTBOE_EN0_M;
    HWREG(IOC_BASE + IOC_O_DTBOE) |= IOC_DTBOE_EN0_EN;

    // select which clock (CKMD) to output on DTB0 (DTB[0])
    HWREG(CKMD_BASE + CKMD_O_DTBCTL) &= ~CKMD_DTBCTL_CLKSEL_M;
    HWREG(CKMD_BASE + CKMD_O_DTBCTL) |= (clockSrc) << CKMD_DTBCTL_CLKSEL_S;

    // enable DTB output
    HWREG(CKMD_BASE + CKMD_O_DTBCTL) &= ~CKMD_DTBCTL_EN_M;
    HWREG(CKMD_BASE + CKMD_O_DTBCTL) |= CKMD_DTBCTL_EN;

Regards,
Ryan

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CC2340R5: LFCI usage, using DIO4 to expose clock