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LAUNCHXL-CC26X2R1: 32 khz crystal adjusting

Guru 18595 points
Part Number: LAUNCHXL-CC26X2R1
Other Parts Discussed in Thread: SYSCONFIG

Hi all,

Software: example "project zero" project. Vanilla, no modifications.

Hardware: cc26x2r launchpad.

The following code modification at the end of function "project_zero_init()" allows my oscilloscope to see the 32 kHz crystal clock signal rerouted to launchpad upper right GPIO 12. Neat! Thanks to Clement.

    IOCPortConfigureSet(12, IOC_PORT_AON_CLK32K, IOC_STD_OUTPUT);
    AONIOC32kHzOutputEnable();

This signal is more or less OK but it is not accurate enough for our purposes. We would like to adjust it per device. So, just before the previous code, we add:

    
    uint32_t subSecInc = 0x20000;
    
    HWREG( AUX_WUC_BASE + AUX_WUC_O_RTCSUBSECINC0 ) = (( subSecInc       ) & AUX_WUC_RTCSUBSECINC0_INC15_0_M  );
    HWREG( AUX_WUC_BASE + AUX_WUC_O_RTCSUBSECINC1 ) = (( subSecInc >> 16 ) & AUX_WUC_RTCSUBSECINC1_INC23_16_M );
    HWREG( AUX_WUC_BASE + AUX_WUC_O_RTCSUBSECINCCTL ) = AUX_WUC_RTCSUBSECINCCTL_UPD_REQ;
    while( ! ( HWREGBITW( AUX_WUC_BASE + AUX_WUC_O_RTCSUBSECINCCTL, AUX_WUC_RTCSUBSECINCCTL_UPD_ACK_BITN )));
    HWREG( AUX_WUC_BASE + AUX_WUC_O_RTCSUBSECINCCTL ) = 0;
    

Unfortunately, this code gets stuck in the while loop. I suspect my offset for AUX_WUC_O_RTCSUBSECINCCTL is wrong, so the combination UPD_REQ, UPD_ACK is never satisfied.

I visited a similar thread but the answer there did not make me go past the loop Disappointed. I attach it here for the sake of convenience for other people.

        e2e.ti.com/.../cc1310-c1310-hang-on-change-rtc-sub-second-increment

My intention is to modify the value subSecInc, for example to 0x20004 to compensate the crystal signal and obtain better precision. This would only be done at the beginning of the code. We would obtain this 0x20004 value or similar via tests by using a frequency counter per device and then load it.

So, my question is twofold:

  1. The register view in Code Composer Studio does not show me any AUX_WUC_O_RTCSUBSECINCCTL, is my offset address right? Please see the #defines I made at the end of this post.
  2. Is this the proper place where to put this calibration code?

Please, let me know your points of view to both questions. The #defines come next.

#include <driverlib/aon_ioc.h>
#define AUX_WUC_BASE                            0x400C6000

#define AUX_WUC_O_RTCSUBSECINC0                 0x0000003C
#define AUX_WUC_O_RTCSUBSECINC1                 0x00000040
#define AUX_WUC_O_RTCSUBSECINCCTL               0x00000044

#define AUX_WUC_RTCSUBSECINC1_INC23_16_M        0x00FF0000
#define AUX_WUC_RTCSUBSECINC0_INC15_0_M         0x0000FFFF
#define AUX_WUC_RTCSUBSECINCCTL_UPD_ACK_BITN    0x02
#define AUX_WUC_RTCSUBSECINCCTL_UPD_REQ         0x01

Have a really nice day.

  • Hello Kazola,

    I hope you are doing well. From the previous post I do not know if we exactly tested an example in this way (so unsure if there are any issues involved). Looks like in order to tune the clock we will need to strictly follow section 16.2.2 of the TRM, " The new sub second increment value must not be changed by AUX until it has received an acknowledgment from the AON_RTC", which looks like what lines 3-7 are trying to do. 

    Did you incorporate "NONSECURE_OFFSET" into the custom address? Similar to the example below. 


    Thanks,
    Alex F

  • Hi 

    Thanks for your time in advance.

    I copied my piece of code from here.

    software-dl.ti.com/.../group__setup__api.html

    I copied the register addresses and offsets from

    https://software-dl.ti.com/lprf/simplelink_cc13x0_sdk/1_30_00_06/exports/docs/driverlib_cc13xx_cc26xx/cc26x0/register_descriptions/CPU_MMAP/AUX_WUC.html#RTCSUBSECINC0_INC15_0

    I don't think I need any NONSECURE_OFFSET because I have never seen this around the forum and also I think my copy paste of the registers addresses are right. But please, please feel free to check such addresses by yourself. I am 90% sure. I don't even understand what NON_SECURE_OFFSET would do. We did it like this because the link above says you have to access the registers from the WUC section.

    The main issue here is we are getting stuck in that loop because of UPD_REQ and ACK. If we could go through it, I think by changing the "subsecsinc" variable would be enough. I also read we might need to write and read a SYNC register, but I also tried this and no luck. Or probably I am doing something quite wrong.

    Could someone at TI try modifying this code to adjust this 32 kHz clock? As I say, the only part I changed is the end of the function "project_zero_init()".

    We will be waiting for your answer.

    Thanks.

  • Hello Kazola,

    Looking at the functions setup files the code you have copied from it is used in the function "SetupAfterColdResetWakeupFromShutDownCfg3" function which has a lot more setup in it. 

    As mentioned previously we currently do not have any official examples, or support for tuning the crystal in this way (or if this is possible); thus, the support from our side is unfortunately limited. 

    Thanks,
    Alex F

  • Hi 

    Thanks for your time and work.

    The user guide says it is possible and we bought about > 3000 of these cc26x2r.  It is not that we have 2 launchpads :) We need to be able to adjust this.

    If you cannot provide the support for this because such low-level code is not your department, could you so kind to escalate this and / or put us in touch with the people that can provide support? We can sign a NDA if this is what is needed.

    I guess if there was another trick to make the device boot directly with tuned subsecinc values, instead of doing it like this on code, this could also work for us, even if we had a slight different file for every device. Is it possible to change this on CCFG or driverlib or someway so it's hardcoded in the flashed code?

    Thanks, I will be waiting for your answers.

    Have a nice day.

  • Hello Kazola,

    I wanted to let you know that l have reached out to the RnD team, currently awaiting their response. I will update this thread when I get a response from them. In the meantime what is the SDK you are currently using, and CCS version?

    Thanks,
    Alex F

  • Great!

    CCS v12.x.

    SDK is 7.40, although I guess your solution will work with any, being such low-level code.

    Thanks!

    We will be waiting for your answer.

  • Hello Kazola,

    I got a response from the RnD team as follows:

    SubSecInc is indeed the register that is adjusted to change the effective update rate of the RTC.

    I would suggest you look at XOSC_LF SWTCXO as implemented by PowerCC26X2_enableXoscLfRtcCompensation(). That adjusts the SubSecInc value as the temperature changes to account for the changing frequency of the crystal oscillator over temperature.

    That will show how to change the SubSecInc value.

    Do you need compensation over temperature, and what the temperature range is? There is a feature in SysConfig for this. 

    Thanks,
    Alex F

  • Hi

    This looks more promising.

    I will check it out on Monday and continue this thread, which I think is becoming very useful to a lot of people.

    Will keep you updated.

    Hope we can "resolve" this thread soon.

    Thanks!

  • Hi 

    I tried this but it did not work.

    I put these 3 lines at the end of a vanilla "project zero".

        PowerCC26X2_enableXoscLfRtcCompensation();
        IOCPortConfigureSet(12, IOC_PORT_AON_CLK32K, IOC_STD_OUTPUT);
        AONIOC32kHzOutputEnable();

    I included the following includes at the top of the file

    #include <ti/drivers/temperature/TemperatureCC26X2.h>
    #include <ti/drivers/Power.h>
    #include <ti/drivers/power/PowerCC26X2.h>
    #include <ti/drivers/power/PowerCC26X2_helpers.h>
    const TemperatureCC26X2_Config TemperatureCC26X2_config;
    

    But the code hangs at the PowerCC26X2_enableXoscLfRtcCompensation().

    I guess they added this code on SDK v7x because of the RTC really drifting when using a 32 kHz crystal so this means this is a known problem.

    I purchased a good frequency counter and the xtal in a launchpad is 32.7684950 and fluctuates a bit.

    We really would be able to adjust this independently of the SDK. So, could you ask this R&D department why the loop at the beginning of this thread / post is stuck?

    By them testing it and fixing it (cannot be more than 5 / 6 lines of code, probably we are missing some register peculiarity) would solve it.

    Thanks.

    We will be waiting for your answer.

    We are running a bit out of time.

    Have a nice day.

  • Hello Kazola, 

    I have reached out to RnD regarding the specific question of why the code hangs in the while loop, awaiting on a response. 

    They also let me know that:

    "if you want to run temperature compensation and add in a single point insertion, they can run similar code to OSC_LFXOSCInitStaticOffset() to set _lfXoscParams coefficient d themselves based on a measurement at a known temperature rather than deriving them from FCFG."

    Thanks,
    Alex 

  • Thanks!