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CC2340R5-Q1: The state of the ports during reset, including POR.

sjmizuta
Intellectual 305 points
Part Number: CC2340R5-Q1
Other Parts Discussed in Thread: SYSCONFIG, CC2640,

Hi, TI_Team.

Could you please provide me with a timeline of the state of each general-purpose port from the reset to the SW application?

I'm considering a 2-chip system with CC2340 and another LSI, and I would like to verify if there are any issues with the interface during reset.

However, I could not find any information in the datasheet and technical references, so I would appreciate it if you could provide me with that information.

 Ex) Reset period: Hi-Z → HW-Boot: Input/Pull-up → ... → SW application(Start)：xxx → SW application(Port Config)：GPIO_Init() Setting values

Additionally, if you have an internal circuit diagram for RSTN and the general-purpose ports, I would appreciate it if you could provide that.

Regards.

  • 0 in reply to Andrew Lugo
    Intellectual 305 points

    Hi,

    Thank you for your response.

    I have checked the contents of the link and TRM.

    Just to confirm, please let me verify if my understanding is correct.

    ”After the reset, once the bootloader is finished, until the pin configuration API, GPIO_init(),

    is executed within the main application, it remains in the OFF state due to tri-state.”

    Is the above correct?

    Also, please provide the next answer.

    Q1.Why do DIO16 and DIO17 have pull-down/pull-up? Is it because of the different internal circuits?

    Q2.Could you provide information about the internal circuits? (Including the RSTN pin)

    Q3.What specific settings are referred to by the statement "the TI bootloader is used then there could

    　　be some pin action depending on how you configure CCFG"? Where can these settings be configured?

    Regards.

  • 0 in reply to sjmizuta
    TI__Intellectual 2410 points

    "”After the reset, once the bootloader is finished, until the pin configuration API, GPIO_init(),

    is executed within the main application, it remains in the OFF state due to tri-state.”

    Is the above correct?"

    This depends on your bootloader implementation. If you look at the Boot Flow diagram detailed in 8.1.1 of the TRM you’ll see that there are 3 boot types (CCFG, FCFG, and No bootloader). Each implementation can take certain IO out of the OFF state during the boot up. If no bootloader is selected then yes the IO remain in the OFF state until the CCFG IO settings are applied.

    Q1. This is because they're dedicated JTAG SWDIO and SWDCK signal pins that have the pull-down and pull-up by default.

    Q2. What specific information about the internal circuits would you like? There are certain things about the circuit that we can not provide as this information is proprietary.

    Q3. The CCFG can be configured in the CCS development tool.

  • 0 in reply to Andrew Lugo
    Intellectual 305 points

    Hi,

    Thank you for your response.

    I understand that CCFG settings can be modified, but is it the same for FCFG as well?

    Based on your response in Q3, we have learned that we are using the default FCFG settings with SysConfig. Please provide more information on this.

    Q1. I have understood.

    Q2. I would like a circuit as shown in the diagram below (excerpt from the CC2640 TRM).

    　　All GPIO pins are necessary, but it would be preferable to have the additional pins if possible.

    　　

    Q3. I have understood.

    Regards.

    　

  • 0 in reply to sjmizuta
    TI__Genius 14385 points

    Hello,

    sjmizuta said:

    I understand that CCFG settings can be modified, but is it the same for FCFG as well?

    Based on your response in Q3, we have learned that we are using the default FCFG settings with SysConfig. Please provide more information on this.

    The FCFG cannot be modified. It is written during manufacturing and is write/erase protected. 

    Do you mind providing more information regarding your second query? What are you curious about?

    sjmizuta said:

    Q2. I would like a circuit as shown in the diagram below (excerpt from the CC2640 TRM).

    　　All GPIO pins are necessary, but it would be preferable to have the additional pins if possible.

    I have reached out to a colleague to find out more and see what we can provide.

    Best,

    Nima Behmanesh

  • 0 in reply to Nima
    TI__Genius 14385 points

    Hello,

    sjmizuta said:

    Q2. I would like a circuit as shown in the diagram below (excerpt from the CC2640 TRM).

    　　All GPIO pins are necessary, but it would be preferable to have the additional pins if possible.

    This is actually the same diagram for the CC2340R5-Q1. 

    Best,

    Nima Behmanesh