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Timing details on the CC2570/71 "SPI" interface?

Other Parts Discussed in Thread: MSP430F2274, CC2571

I'm using a byte-synchronous connection between an MSP430F2274 and a CC2571, which is like SPI, with a few extra control lines.  The timing diagram for this interface (Figs. 13 and 14 of the datasheet, SWRS095A, rev. March 2011) isn't very detailed (besides having the Figure titles reversed :-)  I'm concerned about possible race conditions between the control lines.

For example, when does the !SYNC_ENABLE! line return to its high, idle state relative to the final !SRDY! pulse of a message transfer? Some delay after the leading edge of !SRDY!?  The trailing edge?  How soon after !SYNC_ENABLE! returns high can it go low again to indicate another message from the CC2571 is pending?

Is there a datasheet for a related CC2xxx chip with the same "SPI" interface that would have more details?

TIA,

Mike

  • I'm so sorry since I cannot help you but your question has arised another one in me.

    I know you can suffer from "race conditions" in software like threads within operative systems but can you suffer from race conditions in hardware?

    Well, I'll be glad to know the answer from someone "more hardware" than me.

    Thanks a lot!

  • Hello,

    The reason for the potential lack of details is that there aren't really any hard timing constraints and it is a generic diagram. The timing between events can be affected by a number of factors including sleep state, CPU speed, I/O interrupt responsiveness, and SPI clock speed.

    The leading edge of the SRDY pulse is the trigger, the width of the pulse is not relevant (unless you use MRDY to cause a synchronous reset). The SEN line will go high prior to the checksum being transmitted in either direction. It will remain high until after the checksum has been sent. Typical timing is it taking around 70 us between toggling SRDY and the checksum (or any byte for that matter) being sent. SEN will be high for some time longer than the time to send one byte (transmission time is either 8 us or 32 us for a C7). We have a sample serial driver for byte sync on the MSP430F2274 platform that is pretty robust.

    Let me know if there are any further questions.

     

    Kassandra

  • Yes, , you can have race conditions in hardware, too :-)  (Reminds me of the Cray-1 computer and its immediate descendants -- all the PCB traces and the inter-module connections were differential/twisted pairs cut to exact lengths so the signals would arrive at the right place at the right time.)

    Kassandra, thanks for the info.  Tells me that I need to change my end-of-message interrupt handling a bit :-)

    Mike

     

  • Wow, of course. Silly question sorry :)

    Thanks a lot to all.

  • Hello,

    Sorry to revive an old post but you mentioned "We have a sample serial driver for byte sync on the MSP430F2274 platform that is pretty robust.". Can you direct me to where I might find this driver for the MSP430? Thanks!
  • Hello Anil,

    Please try posting your question in the MSP430 E2E forum.

    Thanks!

    Best wishes
  • Hello JXS,

    Thanks for the reply. I was hoping to find the drivers mentioned for CC2571 which was mentioned on this thread, so I assumed it would be more proper for me to post it here rather than starting a whole new thread about. I also thought it was appropriate to post here since it is CC2571 related.

    Edit: MSP430 forums are very crowded and there doesn't seem to be enough TI employees there to keep track of all threads being posted on there.


    Thanks!

  • Anil,

    Wow! Sorry, but that was a few projects ago.  I'm afraid I don't have any useful code or advice for you.  (And my head is too full of I2C timing issues from implementing a software-driven "bit banging" I2C Slave device in a recent project :-)

    Mike

  • Ah, no worries! It was worth a try. I still appreciate you getting back to me! Good luck on your projects :)