I'm using a byte-synchronous connection between an MSP430F2274 and a CC2571, which is like SPI, with a few extra control lines. The timing diagram for this interface (Figs. 13 and 14 of the datasheet, SWRS095A, rev. March 2011) isn't very detailed (besides having the Figure titles reversed :-) I'm concerned about possible race conditions between the control lines.
For example, when does the !SYNC_ENABLE! line return to its high, idle state relative to the final !SRDY! pulse of a message transfer? Some delay after the leading edge of !SRDY!? The trailing edge? How soon after !SYNC_ENABLE! returns high can it go low again to indicate another message from the CC2571 is pending?
Is there a datasheet for a related CC2xxx chip with the same "SPI" interface that would have more details?
TIA,
Mike