Other Parts Discussed in Thread: UNIFLASH, SYSCONFIG
Tool/software:
Hello TI support Team,
I plan to allocate the bootloader's flash memory block from address 0x00000000 to 0x0000FFFF and designate address 0x00010000 as the application start address.
So I modified "FLASH_BASE" in lpf3_freertos.cmd file.
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#include "ti_utils_build_linker.cmd.genmap"
--stack_size=2048
--heap_size=0
--entry_point resetISR
/* Retain interrupt vector table variable */
--retain "*(.resetVecs)"
/* Suppress warnings and errors: */
/* - 10063: Warning about entry point not being _c_int00 */
/* - 16011, 16012: 8-byte alignment errors. Observed when linking in object */
/* files compiled using Keil (ARM compiler) */
--diag_suppress=10063,16011,16012
/* Set severity of diagnostics to Remark instead of Warning */
/* - 10068: Warning about no matching log_ptr* sections */
--diag_remark=10068
/* The starting address of the application. Normally the interrupt vectors */
/* must be located at the beginning of the application. */
#define FLASH_BASE 0x00010000
#define FLASH_SIZE ti_utils_build_GenMap_FLASH0_SIZE
#define RAM_BASE ti_utils_build_GenMap_RAM0_BASE
#define RAM_SIZE ti_utils_build_GenMap_RAM0_SIZE
#if defined(ti_utils_build_GenMap_S2RRAM_BASE) && \
defined(ti_utils_build_GenMap_S2RRAM_SIZE)
#define S2RRAM_BASE ti_utils_build_GenMap_S2RRAM_BASE
#define S2RRAM_SIZE ti_utils_build_GenMap_S2RRAM_SIZE
#endif
#define CCFG_BASE ti_utils_build_GenMap_CCFG_BASE
#define CCFG_SIZE ti_utils_build_GenMap_CCFG_SIZE
#if defined(ti_utils_build_GenMap_SCFG_BASE) && \
defined(ti_utils_build_GenMap_SCFG_SIZE)
#define SCFG_BASE ti_utils_build_GenMap_SCFG_BASE
#define SCFG_SIZE ti_utils_build_GenMap_SCFG_SIZE
#endif
#if defined(ti_utils_build_GenMap_HSMOTP_BASE) && \
defined(ti_utils_build_GenMap_HSMOTP_SIZE)
#define HSMOTP_BASE ti_utils_build_GenMap_HSMOTP_BASE
#define HSMOTP_SIZE ti_utils_build_GenMap_HSMOTP_SIZE
#endif
/* System memory map */
MEMORY
{
/* Bootloader stored in and executes from internal flash */
//FLASH_BOOT (RX) : origin = 0x00000000, length = 0x00010000
/* Application stored in and executes from internal flash */
FLASH (RX) : origin = FLASH_BASE, length = (FLASH_SIZE - FLASH_BASE)
/* Application uses internal RAM for data */
SRAM (RWX) : origin = RAM_BASE, length = RAM_SIZE
#if defined(S2RRAM_BASE) && defined(S2RRAM_SIZE)
/* S2RRAM is intended for the S2R radio module, but it can also be used by
* the application with some limitations. Please refer to the s2rram example.
*/
S2RRAM (RW) : origin = S2RRAM_BASE, length = S2RRAM_SIZE
#endif
/* Configuration region */
CCFG (R) : origin = CCFG_BASE, length = CCFG_SIZE
#if defined(SCFG_BASE) && defined(SCFG_SIZE)
/* Security configuration region */
SCFG (R): origin = SCFG_BASE, length = SCFG_SIZE
#endif
#if defined(HSMOTP_BASE) && defined(HSMOTP_SIZE)
/* HSM OTP region */
HSMOTP (R): origin = HSMOTP_BASE, length = HSMOTP_SIZE
#endif
/* Explicitly placed off target for the storage of logging data.
* The ARM memory map allocates 1 GB of external memory from 0x60000000 - 0x9FFFFFFF.
* Unlikely that all of this will be used, so we are using the upper parts of the region.
* ARM memory map: developer.arm.com/.../
LOG_DATA (R) : origin = 0x90000000, length = 0x40000 /* 256 KB */
LOG_PTR (R) : origin = 0x94000008, length = 0x40000 /* 256 KB */
}
/* Section allocation in memory */
SECTIONS
{
.resetVecs : > FLASH_BASE
.text : > FLASH
.TI.ramfunc : {} load=FLASH, run=SRAM, table(BINIT)
.const : > FLASH
.constdata : > FLASH
.rodata : > FLASH
.binit : > FLASH
.cinit : > FLASH
.pinit : > FLASH
.init_array : > FLASH
.emb_text : > FLASH
.ccfg : > CCFG
#if defined(SCFG_BASE) && defined(SCFG_SIZE)
.scfg : > SCFG
#endif
#if defined(HSMOTP_BASE) && defined(HSMOTP_SIZE)
.hsmotp : > HSMOTP
#endif
.ramVecs : > SRAM, type = NOLOAD, ALIGN(256)
.data : > SRAM
.bss : > SRAM
.sysmem : > SRAM
.stack : > SRAM (HIGH)
.nonretenvar : > SRAM
#if defined(S2RRAM_BASE) && defined(S2RRAM_SIZE)
/* Placing the section .s2rram in S2RRAM region. Only uninitialized
* objects may be placed in this section.
*/
.s2rram : > S2RRAM, type = NOINIT
#endif
.log_data : > LOG_DATA, type = COPY
.log_ptr : { *(.log_ptr*) } > LOG_PTR align 4, type = COPY
}
===========================================================And CCS displays the following error message when I attempt to update the code in debug mode.
"Cortex_M0P: JTAG Communication Error: (Error -615 @ 0x0) The target failed to see a correctly formatted SWD header. The connection to the target may be unreliable. Try lowering the TCLK setting before trying again. (Emulation package 20.0.0.3178)
Cortex_M0P: Failed to remove the debug state from the target before disconnecting. There may still be breakpoint op-codes embedded in program memory. It is recommended that you reset the emulator before you connect and reload your program before you continue debugging"
Cortex_M0P: Failed to remove the debug state from the target before disconnecting. There may still be breakpoint op-codes embedded in program memory. It is recommended that you reset the emulator before you connect and reload your program before you continue debugging"
Could you please teach me how to solve this problem?
Thank you for your guidance.
