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Original question:

CC2651R3SIPA: Is the state of the DIO pin at power-on (before initialisation) HI-z?

CC2651R3SIPA: How many leak current in DIO pin with no internal pull-up or down resistor?

Toshio Katsura
Prodigy 180 points
Part Number: CC2651R3SIPA

Tool/software:

Hi all
We are using a DIO pin configured as an input with no internal pull-up or pull-down resistor, and an external 1MΩ pull-up resistor connected.

The pull-up voltage is 2.7V, but the voltage measured at the DIO pin is 2.27V.

How many leak current in DIO pin with no internal pull-up or down resistor?
And is this voltage drop considered normal behavior due to the input leakage current?

  • +1
    TI__Expert 6470 points

    From the number you have given,

    2.7V - 2.27V = 0.43V

    0.43V/1MΩ= 0.43uA, which is normal

    From the datasheet pullup current is 73uA and combined with the fact that the default pullup resistor is about 10k. This number makes sense because the resistance is 2x less order of magnitude

  • 0 in reply to Bun Kuch
    Prodigy 180 points

    Thanks.

    I have one more question.
    > 0.43V/1MΩ= 0.43uA, which is normal

    Could you let us know max leak current from input pin with no internal pull-up or pull-down resistor?
    If the maximum leakage current exceeds 1.08 µA (1.08 V / 1 MΩ), this input cannot be considered as having Vih = 1.08 V.

    Regards.

  • 0 in reply to Toshio Katsura
    Prodigy 180 points

    Sorry, I sent wrong cal.
    If the maximum leakage current exceeds 1.62 µA ((2.70V-1.08 V) / 1 MΩ), this input cannot be considered as having Vih = 1.08 V.

    Thanks

  • 0 in reply to Toshio Katsura
    TI__Expert 6470 points

    Input pins should not be floating as it can oscillate and the worse case at 0.5Vdd, where both CMOS gates are on, you can draw anywhere from uA to mA depending on temperature, process, and how the electrons are feeling that day. It is difficult to measure. Inputs should also be pulled up or down.

  • 0 in reply to Bun Kuch
    Prodigy 180 points

    Thank you for your reply. We agree your advice.

    As you advised, we have connected external pull-up resistors (1 MΩ) to the input pins. Internal pull-up or pull-down resistors are not used.

    The 1 MΩ resistors are selected to minimize power consumption.

    We are concerned that if the maximum leakage current flows through the 1 MΩ pull-up resistor, the input high-level voltage may drop below the specified Vih threshold.

    Could you please provide the maximum leakage current of an input pin when no internal pull-up or pull-down resistor is used?

    Regards.

  • 0 in reply to Toshio Katsura
    TI__Expert 6470 points

    We do not have this measurement because inputs are always and should always be pulled in the case of a true no pull resistor.

    Your concern about Vih is separate, assuming you're using 2.7V as VDDS, the Vih threshold is 0.8VDDS = 2.16V, which means you would have drop 0.54V across the 1MΩ resistor implying a 0.54uA must be drawn to cause this issue. If you use a lower resistance, then you're allowed to draw more current before you reach the Vih threshold.

  • 0 in reply to Bun Kuch
    Prodigy 180 points

    Thank you for your comments.

    I mislead about Vih, now I can understand your advice.
    Thanks.

    We'd like to use 1M ohm or less higher external pulled-up resistance and disable internal, due to decrease power compression.

    Could you advise us whether using a 1MΩ external pull-up resistor would still meet the Vih specification?

  • +1 in reply to Toshio Katsura
    TI__Expert 6470 points

    1MΩ is close and I would not recommend it. You were pulling 0.43uA and the threshold is 0.54uA. Try 100k because it would give you a balance between lower current and higher threshold.

  • 0 in reply to Bun Kuch
    Prodigy 180 points

    Thank you for your reply, and we will check and consider it.

    Regards.