How to detect battery level while using CC2540 and TPS62730

Hi Karl,

In EVM  CC2541+TPS62730  reference design. Port1 pin2 was used  to control TPS62730.

I am wondering if it possible to add  P1.2 control in function "static uint8 battMeasure( void )", set P1.2 to  LOW before ADC  measurement  and set P1.2 to High after  measurement ?

Best regards,

George

Karl T. said:

I would recommend using an external resistor divider to divide it down to be safe, and then measure that voltage with the ADC.

Karl,

Wouldn't any sensible resistor divider draw more average current than any other part of the design?  E.g. 2x 100kOhm resistors would draw 15uA.  Also, ADC input impedance is stated to be 197kOhm that calls for low impedance source.  Resistor divider has too high an impedance (unless bypassed with a cap.)

How about using two diodes in series to drop Vbatt by 1.4V feeding it directly into an ADC pin?

Leo

I wouldn't use diodes as the forward drop is going to be quite unpredictable (changes with temp, diode-diode variance). Also, with only several uA of current the forward voltage drop will be much lower than 0.7V, and is going to change quite significantly with changes in current. 

A better solution is to use a PCH fet as a high-side switch (you wont be able to connect the gate direct to an I/O pin due the Vbatt - Vcc voltage difference). Connect the PCH source to Vbatt, PCH drain to your low impedance (10k or so) divider. Connect a pull up from Vbatt to the PCH gate. You will need an NCH fet to pull the PCH gate low to make a measurement.

I use low side switching only to reduce part count with two 470k resistors and a 1nF cap with the divider ground to an I/O pin. To disable the divider the I/O switch is set to input. Most of the time the battery voltage is higher than the VCC + 0.3 clamp voltage, so a small current flows into the I/O pin. This does not affect the overall current draw as it feeds into VCC via the internal clamp and the voltage regulator supplies less current to VCC to compensate. The 1nF cap is important as provides a low impedance for the ADC, the catch is that the divider needs to be enabled for around 1ms before the measurement to ensure its voltage has stabilised. With the above I get good voltage detection accuracy and around 4-5uA draw from the battery in sleep with RTC including regulator.

Thanks Eng for sharing that part of your design. 

However, it's not still clear to me where the 470K resistors and the 1nF cap are. The drain of the PCH is connected to a voltage divider (2 10k resistors) and its middle point is connected to the ADC input.

Now, in order to drive the PCH fet you use a NCH fet with the source connected to ground and the drain connected to the gate of the PCH. Right?

Sorry but I can't see when the current flows through the clamp nor where to place the 470K resistors plus the 1nF cap. I'd very much appreciate if you could please clarify it.

Regards,

D.

Eng meant this typical divider with controlled pull-down.

[BATTERY]------{R1 470K}----+----{R2 470K}----> PORT PIN CTRL

                            |

                            +-----------------> PORT PIN ADC

                            |

                           === C1 1nF 

                            |

                            GND

Make PORT PIN CTRL output low level during measurement and output high during sleep.

Clamping diode current flows from battery through R1 and into an ADC pin then via internal diode and into Vdd, powering the circuits in standby.  Forcing current through parasitic diodes is how typical lethal CMOS latchup is started so keep resistor values high.

Leo

Thanks Leo for the answer.

Are you sure that's what Eng was meaning?  He mentioned 10K divider and two mosfets...

Also, if two mosfets are used I can't really see amu current flowing to the IO control pin.

Regards

Ok forget my last post. I missunderstood him, he was talking about two options and actually not using the mosfets approach. Rather, he is using your schematic...

Thanks and sorry

D.

Eng351 said:

I use low side switching only to reduce part count with two 470k resistors and a 1nF cap with the divider ground to an I/O pin. To disable the divider the I/O switch is set to input. Most of the time the battery voltage is higher than the VCC + 0.3 clamp voltage, so a small current flows into the I/O pin.

Doesn't it exceed the absolute maximum rating for an I/O pin of (VDD+ 0.3V)?

You say that the current back to VCC through the internal clamp doesn't affect the overall current draw. Does it apply also for LDO or only when using DC/DC converter? I want to read my LiPo battery voltage but would like to avoid the 2 FET and 3 resistors approach.

Thanks!

Daniel A. said:

Doesn't it exceed the absolute maximum rating for an I/O pin of (VDD+ 0.3V)?

You say that the current back to VCC through the internal clamp doesn't affect the overall current draw. Does it apply also for LDO or only when using DC/DC converter? I want to read my LiPo battery voltage but would like to avoid the 2 FET and 3 resistors approach.

Specifying maximum i/o pin voltage as Vdd+0.3V is another way of saying "current flowing into an i/o pin should be limited to a value that causes less than 0.3V drop across parasitic/clamp diode."

If you can control the current  you can control the voltage drop.

Leo

Thanks Leo.

I've tried to find out the characteristics of the parasitic diodes inside the CC2540 with no success. What's the typical max amount of current to not exceed the 0.3V?

Also, in the case of using an LDO: is this current flowing to VDD through the clamp diode not affecting the overall current draw?

Dani

I'm a little late coming to this, but I'm having the same issue measuring battery voltage on the microcontroller powered by the TPS62730 regulator. I'm just starting the schematic, so I haven't had a chance to try this yet; but why can't we just power down the regulator with the ON/BYP signal, and wait a millisecond or so for output to settle up to the battery voltage (2 ohm resistance into <10uF capacitance should settle fast). Then we can take a normal ADC reading of internal Vcc.

I'm using the CC430, so drawing <1mA across the 2ohm resistor would be <2mV error. Other uC's could draw around 5mA across 2ohm resistor for a 10mV error; but this can be compensated for in software if needed.

Any reason I can't use this approach and save the resistors and I/O pins?

Hi Daniel,

What is really going to do damage is excessive current through the diode - if you hit 0.3V that's ok, diodes are happy to run in saturation. I do not know what the maximum current is but I would say in the order of mA. In practice if the divider resistance is high enough i.e. several hundred kilo-ohms, the maxim current will be in the order of uA. For example if the divider top resistor is 470k, Vdd = 3.0V, Vbatt = 4.2V, you will get a worst case of (4.2 - 3.0)/(470K) =  2.55uA. In practice it will be a bit less than this due to the parasitic diode forward voltage drop at that particular current (small due to low current).

The above 2.55uA flowing into VDD via the clamp diode will sum together with the VDD supply entering the CC2540. As a net result your LDO will need supply 2.55uA less to maintain the 3.0V rail, and therefore this will not affect overall current.

Imagine connecting a diode and high value resistor from the vbatt terminal of the regulator to the output of the regulator. The above has the same effect.

I have achieved a battery current of 3.1uA in sleep mode with 32.768 xtal running. I have however found the voltage measurement described above requires some calibration. Even with the 1nF cap there is still some voltage drop on the divider when taking a sample. Unfortunately I was in a bit of a rush and overlooked the relatively low impedance of the ADC. On the next versions I will use a high-side switch and smaller resistor values.

Daniel A. said:

Thanks Leo.

I've tried to find out the characteristics of the parasitic diodes inside the CC2540 with no success. What's the typical max amount of current to not exceed the 0.3V?

Also, in the case of using an LDO: is this current flowing to VDD through the clamp diode not affecting the overall current draw?

Dani

Hi Chad, I don't see a reason why your approach wouldn't work. The TPS62730 solution is only going to work for a 3.6V battery whereas the discussion above is related to using a LiPo rechargeable battery which is up to 4.2V.

The LDO solution proposed is for a device which spends most of its life in sleep mode and transmits infrequently. The LDO solution trades off RF and run power efficiency for Sleep mode current / cost. 

If anyone comes across a TPS62730 -like solution with an ultra low current LDO instead of the 2R resistor that can handle 4.2V I'm all ears :)

Leo Bodnar said:

Eng meant this typical divider with controlled pull-down.

[BATTERY]------{R1 470K}----+----{R2 470K}----> PORT PIN CTRL

                            |

                            +-----------------> PORT PIN ADC

                            |

                           === C1 1nF 

                            |

                            GND

Sorry for getting back to this again.

I have implemented the diagram above and after enabling the divider making PORT PIN CTRL low for 10ms and then reading on the ADC pin, I always get like 0.3V less than the actual voltage on that PIN.

What am I doing wrong? Should I increase the capacity of C1 - and to what extent?

Many thanks

Daniel

The 0.3v is due to the loading of the ADC pin. Have you looked at the signals on a scope? This can be reduced by decreasing resistors, increasing C1 to 10nF and putting the ADC into its lowest possible resolution. Try to experiment with say 220K resistors and a 10nF cap and see what sleep current you get. I mentioned this problem above, hence the suggestion of a high side switch.