CC2745R10-Q1: How can I keep SPI POCI to High when in use?

Hi Island,

Thanks for your question regarding the SPI interface on the CC2745R10-Q1. I’d like to help clarify what you’re seeing, but I’m a bit unsure about part of your description and would appreciate a little more detail so I can give the most accurate guidance.

In standard SPI operation (mode 0,0), the POCI line is used purely for data transfer. The CC2745R10-Q1 acts as the SPI controller, and the sensor (peripheral) is responsible for driving the POCI line with valid data during each SPI clock cycle. This line will toggle between high and low depending on the actual data bits being sent.

You mentioned that the POCI (MISO) line is pulled down during SPI operation, but you’d prefer it to stay high, and for the external sensor to pull it low only when transferring data. From how that’s phrased, it sounds like you might be expecting the line to act like a “data ready” or interrupt line if it is not being used as POCI. Are you perhaps looking for a way to detect when the sensor is ready to send data? If so, this would typically be done using a separate GPIO line, often labeled something like “data ready” or “interrupt” (e.g., the sensor pulls the line low when new data is available). This would let the controller know when to start an SPI transaction, and may be more aligned with what you’re describing.

However, please clarify if your main concern is that you would like to reuse the same IO as both a data ready line and POCI.

Best Regards,

Cash

Hi Ramos,

Thanks for your reply. I think the picture can describe what I expected and what I got. The reason I expect is that I want to save power by entering directly into "data ready" as you mentioned and I have no extra IO to use. If it CC2745 cannot made it, I need to put a pull-up resistor to the POCI on my board, but it will cost extra current.