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CC2651R3SIPA: External clock input and reset release sequence

Part Number: CC2651R3SIPA

Tool/software:

We will use a 32kHz input from an external oscillator and a reset input from an external reset IC as follows.

In our current power-up sequence, we ramp up VCCS to 2.5V and then release the reset. After that, the 32kHz clock signal becomes stable.
Is there any problem with this clock stabilization sequence?

Or should the 32kHz clock input be stable before releasing the reset?

  • Hi Toshio !

    I will invite our expert to help you.

    Kind regards,
    Maxence

  • Dear Maxence,

    Thank you, we are looking forward to receiving reply from expert.

    Regards.

  • Hi,

    It is preferable to have a stable 32kHz clock source before the device is released from reset. The reason is that, during the device boot, it will try to use the clock source configured in its initialization code and might fail in case this clock is not present.  

    One alternative is that you can perhaps hold the reset signal for this module just in time the 32kHz clock is present. Our device does not have a maximum limit on the time the reset line is asserted (section 8.15.1 of the device datasheet).

    Details about the Power, Clock and Reset system can be found at the chapter 7 of the CC2651 Technical Reference Manual. 

    Hope this helps,

    Rafael

  • Hi,  Thank you for reply.

    I checked chapter 7 of the CC2651 Technical Reference Manual. and I have additional questions.
    After reset released, which clock source CC2651R3SIPA be used before loading Customer Configuration?
    - 48 MHz RC oscillator
    - 48 MHz crystal oscillator
    - 32 kHz RC oscillator
    - 32.768 kHz crystal oscillator
    - 2 MHz RC oscillator
    - 32.768 kHz external oscillator from DIO

    Should all clock source start vibration before reset released?

    And can we change 32kHz clock source from internal RC oscillator to external oscillator dynamic from DIO after loading Customer Configuration?

    Regards.

  • Hi Toshio, 

    Please apologize for the delay; I was sidetrack for the past weeks. 

    The initial clock is the 48 MHz RC oscillator, which kickstarts the external 48 MHz crystal if it is configured in CCFG and fitted to the board. After that, the CPU starts its normal boot process. 

    The selection of the 32kHz clock source happens during the device initialization after reset, by reading the appropriate CCFG registers during startup. There is a mechanism to detect a clock loss (section 7.7.1.1 of the device TRM) but not to dynamically change it. 

    Hope this helps,

    Rafael

  • Thank you very much. All my concerns have been addressed. We'll close this ticket.

    Regards,